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Recent content by user0088

  1. U

    random file name in verilog-a

    I will really appreciate any help in this regards.
  2. U

    random file name in verilog-a

    Hi all, How to create a file with random name in verilog-a ?
  3. U

    Differential Resistive DAC structure

    Hello, I am looking for a differential resistive DAC in literature/papers, which - has single Vref reference voltage - common-mode of output differential signal is CM -and CM > Vref I didn't find any information/example/paper. Could you please show me such examples? Thanks.
  4. U

    [SOLVED] DAC: question regarding spectral analysis

    Could you please advice how to put correct simulation settings for performing FFT. Which strobeperiod should be used for DAC ?
  5. U

    [SOLVED] DAC: question regarding spectral analysis

    Hello all, I have designed DAC, which last stage is SC filter. The FFT analysis of SC filter output shows that SFDR is about 80dB (time interval - from A to B). Modeling is performed in Cadence design environment, strobeperiod=Fclk/10 is used, where Fclk is clocking frequency of SC Filter...
  6. U

    OA specifications used in SC Filter

    What you meant? It isn't clear for me.
  7. U

    OA specifications used in SC Filter

    ??? If input data frequency is ,for example, 10MHz, what is bandwidth of OA (at -3db) ?
  8. U

    OA specifications used in SC Filter

    Hello all, Could you please advice how to choose OA specifications (dc gain, bandwidth, settling time, etc) used in SC Filter. Thanks.
  9. U

    about current steering DAC

    What kind of effects do you mean?
  10. U

    about current steering DAC

    Re: advantages of current steering dac Hello all, Please share your opinion in this regards, i.e. how to define specifications (dc gain, bandwidth, settling time, etc) for OA used in DAC's Filter. Thanks in advance.
  11. U

    INL/DNL measurements for Sigma-Delta DAC

    Could you please advice how to measure INL or DNL of the Sigma-Delta DAC. Please note, that the input signal frequency is Fin, but the output signal frequency is OSR*Fin. Thanks.
  12. U

    Capacitor nominal in switched-capacitor filter

    How to define capacitor nominal in switched-capacitor filter? I have calculated capacitor rations for a some structure of SC filter, where exist 4 capacitors (C0, C1, C2, and C3). I got, for example, C1=0.1*C0, C2=0.2*C0, and C3=0.3*C0. How to define nominal of base C0 capacitor? What are the...
  13. U

    current-source mismatch calculation in cadence

    How to calculate mismatches in current sources at cadence design environment. How perform the simulation? It is necessary to get comparison of different structures for current sources in terms of mismatches. Thanks.
  14. U

    [SOLVED] Negative capacitor value in switched capacitor filters

    Please find attached file. Capacitors' values are shown in the last page. It is not clear, how to perform "-" value in circuit, for example in cadence.
  15. U

    [SOLVED] CMOS Transmission Gate

    When A=!B, then F=(VDD-Vth) instead of strong VDD.
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