Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Recent content by useless_skew

  1. U

    Doubt in Functionality of DDR3

    Memory controller can operate at a higher clock frequency. But DRAM core cells can operate only at limited frequency. In single data rate SDRAM, the physical interface was acting at the same frequency as the DRAM memory cell and the IO. But in case of DDR SDRAM, the data rate was doubled (DDR...
  2. U

    what are remedies for IR drop

    If the IR drop is concentrated at one particular location, spread out the cells in that region if possible.
  3. U

    Queires need urgent solution for it ,please do help me out

    Re: Queires need urgent solution for it ,please do help me o
  4. U

    How can I know if my setting in SDC file is good or not?

    SDC is purely design specific. The clock definitions, uncertainty values, case setting, input/output delay specifications, timing exceptions all depend on our design, the number of clocks you have and the frequency of those clocks. SDC can be check for syntax errors by loading it (in tools like...
  5. U

    low power design in UPF

    To use the low power options of the tool, a low power license is required. Information about UPF and UPF tech docs - http://www.unifiedpowerformat.com/technicaldocuments.html Low power methodology manual is available in net for download.
  6. U

    How to learn tcl-scripting?

    Learning alone doesn't help. Try automating your tasks by scripting. Practice file handling, looping, regular expressions, array usage, hash (in PERL).
  7. U

    Does clock skew leads to Setup Violations or Hold Violations

    Re: Does clock skew leads to Setup Violations or Hold Violat With zero skew, there is won't be any hold violation. At zero skew, Tcq + Tcomb should be greater than Thold. Even if Tcomb = 0, Tcq will always be greater than Thold.
  8. U

    Which metal layers we use for Clock Tree Synthesize?.

    Re: CTS Route Metal Generally, the top-most layer is reserved for the power routing. The layer that is immediately below the top-most metal layer can be utilized for clock routing. I am not sure whether clock routing can share the top-most layer with power routing. Can somebody clarify this?
  9. U

    spice netlist from verilog code

    To generate a spice netlist, we need parasitic information for the nets as well. Just using the spice models for the cells won't give accurate results. If you have the LEF and DEF, you can use Starxt to dump the spice netlist.
  10. U

    How is IR drop analysis done?

    Re: IR drop analysis Blastrail/Quartzrail can do the IR drop analysis. We are usually interested in the % of vdd/vss drop. Also there are other tools available from Synopsys and Cadence to do the IR drop analysis.
  11. U

    just need a clarification on setup time fixing

    Re: doubt on timing It can fix the setup time but it will introduce some undesirable clock skew affecting the timing of the next stage.
  12. U

    Script for sending email with attachment using Linux console

    Re: mail using perl Try the following section of code (perl script): open (MAILFD, "| /usr/lib/sendmail -it") || die "Cannot run sendmail... $!"; print MAILFD "From: <your mail id>\n"; print MAILFD "To: <recipient id>\n"; print MAILFD "Subject: <subject>\n"; print MAILFD "<message body>"...
  13. U

    What is called TDL generation?

    Heard that we can generate TDLs by giving .VCD files to some tool as input.

Part and Inventory Search

Back
Top