Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by usaid

  1. U

    Clock Skew Minimization

    Check these papers on clock tree synthesis......
  2. U

    Clock Skew Minimization

    Check this one....
  3. U

    Getting job in VLSI field

    list of companies involved in VLSI design in India: https://usaidabbasi.tripod.com/id23.html
  4. U

    the difference between ungroup and set_flatten commands

    design compiler ungroup the ungroup command removes the hierarchy in the design (netlist) and make it flat.. you can use set_flatten command (options are true and false) to enable and disable this behavior during logic optimization (during compile)... By default it is set to be false...
  5. U

    self aligned structure

    when you diffuse drain and diffusion areas,they automatically aligns beneath the polysilicon(as polysilicon acts as a mask)..This is called self aligned structure..
  6. U

    Suggestions of materials about crosstalk

    Re: Crosstalk check the following links:
  7. U

    Image compression using FPGA

    consult the following site: http://www.digilentinc.com/Education/Tutorials.cfm?Nav1=Education&Nav2=Tutorials
  8. U

    Can anybody explain me what is meant by transistor sizing?

    Re: Can anybody explain me what is meant by transistor sizin sizing is nothing but playing with the width of the transistors
  9. U

    Difference betwen analyze -f verilog and read_verilog in DC

    dc read_verilog Elaborate allows you to specify architecture, and allows you to override parameter values...
  10. U

    What are electromigration and latch-up?

    Re: cmos https://en.wikipedia.org/wiki/Design_Exchange_Format
  11. U

    which tool is easier to learn?

    Magma blastfusion is easier to learn...
  12. U

    what are level shifters?

    these are typically used in low-power design flow where core and IOs are operating at separate voltages...
  13. U

    Explanation of the NBTI process

    Re: NBTI NBTI stands for Negative Bias temperature instability.This is due to the trapping of holes at Si/SiO2 interface.
  14. U

    What is the STI process?

    Re: STI STI(Shallow Trench Isolation) is the process used for physical separation of devices in the Chip.It had replaced the older LOCOS process as it offer more planar surface than LOCOS.Also it is free of undesired phenomena like Birdbeak
  15. U

    What is the effect of STI stress on mobility?

    Re: STI stress Mobility degrades as the carriers have to move in a more stressed condition,.
See more

Part and Inventory Search

Back
Top