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Usually, you just need ~200-mV overdrive for the current mirrors. For the amplification transistors and the cascode transistors, you can use small overdrive, even pushing them to subthreshold, if you don't have other special concerns.
We're going to tape out in TSMC 2p4m 0.35 um process through MOSIS. May I know if anyone has experience in this process with MOSIS? If so, when you designed the circuitry, did you use the third-party PDK (NCSU PDK, for example) or the PDK from TSMC?
Thanks,
upvl
Re: 1.2V 50MHz GB Op amp
How much gain do you need? 20dB? 40dB?
GBW=gain*band, which is the most critical spec for Opamp design. If it is used in continuous-time amplifier or filter, you could use some tricks to achieve the high bandwidth. But, it's for ADC, you may have to consume significant...
You could use finger caps by metal or MOSFET caps (with ESR though) . A good way is to stack all kinds of caps available:
1. Bottom: MOS caps
2. Middle: finger caps
3. Top: MIM caps
Also, the finger caps and MIM caps can be placed upon the regulator if it doesn't use top layer metals.
Still...
Officially, I would say no. However, the foundries tend to be conservative about the break voltage of the transistors. In some specific applications (like power amplifier) , you could and sometimes have to use higher voltage drop on the transistors to achieve the speficications. No one without...
If you just wanna know thermal/flicker noise for most linear circuits, you could simply use "noise" simulation. I'm afraid that DFT is just for the simulation of quantization noise for sampling circuits.
Re: cancelling the process variation effect of 50ohm resisto
The foundry will tell you the resistance will vary up to 20% in different technology corners and temperatures. But, actually, the variance won't be so much according to my experience. It's generally about 5% in some mainstream...
the latter, of course. it's accurate and you can even put the mismatch information in the simulation. it's rather slow, though.
the former is fast but can only give you a rough feeling about the extreme case, but can you really know which combination of the PVT is worst case? Especially...
Re: Connecting two high gain fully differential opamps &
offset cancellation
it's necessary for high-gain amplification, otherwise you may have to increase the size of your input diff. pair to make a ultra-low-offset input.
anyway, it finally depends on how large the gain is. If the gain is not...
Re: FOLDED CASCODE OPAMP DESIGN ....FACING PROBLM IN BIASING
I think I may give you some suggestions:
1. The bias current for the top two PMOS current (7&14) should be the sum of the current flows into the amplifier stage and the rest cascode circuits. You set wrong current, so you can't make...
Hi, I'm currently working on a 10b sar adc with low speed. I use the attenuation cap in the 10b cap dac to decrease the chip size, but I'm kinda worried about the match of the unity cap and the attenuation cap, which is 32/31 of the unity cap. Actually, I don't really have to achieve 10b ENOB...
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