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Hi,
In my project I am working on IEEE based .topic is ANALOG IMPLEMENTATION OF A SIGMOIDAL FUNCTION USING CMOS IN 90nm TECHNOLOGY
but we are trying to implement in 180 nm cadence.
concept is that they are following is
[PLEASE CHECK ATTACHED PAPER NAMED P1]
current is the input and voltage is...
hi
for a transistor in 90 nm if the L=0.2 micro meter and width is 4 times of length to achieve required transfer characteristics what could be the changes to be made in 180 nm.
sir,
I dint get PDK
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Sir ,
In our college there is no availability of any other software other than cadence 180 nm
so we are working in that
here in that paper they have used 0.2 micro meter length and they have used different width for different transistors
sir how can I...
hi,
we are implementing the IEEE paper of ANALOG IMPLEMENTATION OF A SIGMOIDAL FUNCTION USING CMOS IN 90nm TECHNOLOGY .here they are making use of 90 nm. but we are trying in 180 nm in cadence .we could able to finish 25 percent of work but choosing w/l ratio is challenging part
pls can some...
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