Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Recent content by ultimate_kc

  1. U

    Microblaze debuggig.

    Hi all, Is it possible to debug firmware written in microblaze without connecting to a hardware. Thanks in advance.
  2. U

    Microblaze simulation using NCSIM

    Hi, I would like to simulate a microblaze system using NCSIM. Can anybody suggests me how to associate elf files that is generated from SDK and corresponding libraries to compile Microblaze system. NB: I have simulated a microblaze system in vivado simulator. Regards
  3. U

    Do we need a DDR module for video scaling in fpga?

    so its is mandatory to have a storage (either DDR or external storage of 32 MB)? My question is that can we do scaling or cropping without storing it like other ip cores such as Edge enhancement or color correction matrix.
  4. U

    VHDL code error for assigning value to signal

    You cannot assign array like that. it will show an syntax error For declaring an array of 15rows and 15 coloumns : type sample is array (15 downto 0) of std_logic_vector(15 downto 0); signal sample_1 : sample; if clk = '1' and clk'event then i <= i + 1; sample(i) <= data_in; end if; i...
  5. U

    1080P video standard?

    thanks for your valuable reply. it was really informative.. before this valuable information i too searched as mentioned above. but it was access denied.
  6. U

    1080P video standard?

    hello, i would like to know about 1080 video standards. To be specific, SAV(Start of active video) EAV(End of active video), Start of inactive video, end of inactive video... Thanks in advance
  7. U

    Do we need a DDR module for video scaling in fpga?

    Thank you for your response. :smile: i am using 1920*1080 P as input to video scalar ip core. my bram is 64K. can i do scaling or cropping?
  8. U

    Do we need a DDR module for video scaling in fpga?

    Hello, I want to use video scalar ip core in sp605 evaluation board. My doubt is whether we need a DDR module for video scalar ip core? Thanks in advance :)
  9. U

    [SOLVED] Converting Bi directional to single directional input

    Hi, I have a bi directional signal, say SDA in Top module. i want to convert this bi directional signal as input and output in the top module and feed into different sub modules. Is there any primitives in VHDL for this conversion? Any help will be thankful.:-)
  10. U

    delay calculation in vhdl

    First create a signal (for example - delay) then pass values to this delay in process or where ever u need to pass signal delay; delay <= "011" if delay /= "00" then delay <= delay - 1; else delay <= "111"; end if;
  11. U

    How to read ram in test bench?

    Hi all, I have a ram of 32 bit width and 4 bit depth. i am using simple dual port ram. i have written data into the ram. now i want to read this data from test bench. can i use for loop for reading?

Part and Inventory Search

Back
Top