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:) Flipping the PMOS not solved the problem (that was a mistake in the simulation, but in the real circuit it's right - Drain is the output, Source is to the left). In simulation when flipped the result is the same. I have some success only if R1 is way too low - about 430 ohms. What is the...
Guys, I need some help with my circuit which I have attached below...
My circuit is intended to be a very cheap solution of a transmitter-receiver channel - the receiver is comprised of R1 and D1 and the rest components are the transmitter.
The problem is with the gate voltage of the...
@rajaram04: can you, please, share your experience with the hand detection device. I will be thankful.
I want to design similar device - I have built a relaxation oscillator using an inverter (7414), one cap. and a positive feedback resistor and have connected an antenna to the input of the...
Yes, you are right of course. I do not complain that the MAX1771 is not working, I just didn't expected the transistors to be damaged. The idea is a bit crazy, I know that, but I wanted to be able to move the motor for 1-2 sec and than wait 0.5-1 min before do it again. The motor is a stepper...
Hello,
I need to boost a 2 cell rechargeable battery to 12V / 500mA output. This will be used to power a small stepper motor, but for short time periods - few steps, few seconds pause, next few steps, next few seconds pause. The cells will discharge of course, so I need the device to operable...
Hi all!
New in the ethernet comm. field...
I need to design a PoE Ethernet and started a research.
Can anyone provide me with information about differences with RJ45 connectors with integrated magnetics that are capable for PoE? I'm checking the Tyco Electronics website (this **broken link...
Hello All!
Is anybody aware of where can I find the "University of Guelph Floating-Point Arithmetic" library - "uog_fp_arith"? Is it free or not? How can I use it?
Google seems to be not very friendly regarding this information.
Besides, I am interested in any HDL package (preferably in...
I found the nice code by nand_gates here. So thank you!
The code works fine, but unfortunately I'm too stupid to discover what is happening inside it.
Can anyone explain this code in more details? Please!!!
What is the main idea in the algorithm?
What if I want to change the bit width for...
Hi!
Well, thank you for the answer. But it didn't helped me.
The coding itself is not a problem. And the parallelism - it's the think FPGAs are the best in. I would like to hear about the algorithm.
It's not hard to find information about the Bezier curves - simply looking at Wikipedia. But it...
bezier interpolator
Hi!
I am working on a small CNC project. I want to expand it with a curve interpolator.
Does anybody is aware of the FPGA point of view of how to design a Bezier curve with programmable logic?
Suppose I have four reference points, like in figure: . How to calculate the...
Hello guys,
Is anybody aware with the problem of pattern alignment? I'm in torment with the task of fingerprint recognition. Mainly this task can be divided as follows:
1. Reading from the sensor (swipe sensor) and construct an image (from different slices) of the finger.
2. Preprocessing...
Hello people,
I'm trying to dive into deep waters. I'm trying to implement (more correct I'm looking for more information at this stage) some basic (for the moment) neural network with FPGAs. I am very interested in how others are doing it. But found almost no free information - basically some...
evita verilog how to use
Hi, nczx,
First of all, Matlab is completely different tool (actually a tool) than Verilog (it's a language). Verilog is a Hardware Description Language (HDL). There are many such languages like VHDL (it stays for Very High Speed Integrated Circuit (VHSIC) Hardware...
coolrunner ii troubleshoot
Hi, bansalr,
Thank you for your reply :)
I tryed to put some timing constraints and the error is gone. It worked :)
But, since I'm relatively new to Verilog (and even to digital electronics in some aspects) I am a little bit confused - there are so many settings...
xilinx timespec
Hello, Verilog gurus,
I'm experiencing the following problem:
I try to implement a design on Xilinx CoolRunner II using ISE WebPack 7.1.i_04. The design is written in Verilog. The design uses 1.8432MHz clock which is internally divided when needed to ~20Hz. Behavioral...
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