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I designed capless LDO and measured it.
There are two same LDOs.
One output is floated(just connected to pad), and the other is connected ESD NMOS.
Hmm. measured data is different!
I don't know why... Anybody can help me?
w/ ESD IO NMOS w/o ESD IO NMOS
BGR LDO output...
I have 9 stage CMOS ring osc. (Target : 20MHz)
But, this circuit was design by another engineer, not me.
1. How can I get study materials about this circuit?
2. In measured data, this osc operates about 24MHz.(22~26MHz)
So, How can i control or trimming this circuit to meet the target...
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