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Oratie,
Thanks for your advice. After I added an inverter, the delay was much less than before, but still about 50% larger than the HSPICE simulation. I found that the wire load model in PT only reflects the capacitance in the spice netlist, and there is no resistor in the netlist. I'm not sure...
The supply voltage of input A is in output_stim.sp，
vA A 0 pwl(0.0ns 1.1
+ 4.9988ns 1.1
+ 4.99905ns 1.045
+ 4.9993ns 0.915833
+ 4.99955ns 0.77
+ 4.9998ns 0.641506
+ 5.00005ns 0.527042
+ 5.0003ns 0.423929
+ 5.00055ns 0.33
+ 5.0008ns...
I found very large delays between port A and pin INV1/A and between port ZN and pin INV1/ZN by verifying the inverter waveforms in PT-GUI. I confirmed that there is a wire capacitance via schematic in PT-GUI.
I tried adding this line of codeset_ideal_network [get_ports {A ZN}]
After executing...
Here is the spice netlist I extracted from PT. It includes the main circuit and transistor models. I omitted a lot of unnecessary information, such as comments.
.model NMOS_VTL nmos (level = 54
+tnom = 27 epsrox = 3.9
+eta0 = 0.006 nfactor = 2.1 wint = 5e-09
+cgso = 1.1e-10...
Simulations show that the results of PT are several times larger than HSPICE.
I've tried a few ways to solve it, but I found something very strange.
If I apply a clock to the input of the inverter in this way
set CLK_PERIOD 5
set CLK "A"
create_clock -period $CLK_PERIOD [get_ports $CLK]...
Dear Oratio，
Yes, the subcircuit netlist contains only RC parasitics, and the header file only contains the transistor model. Here are the details about my subcircuit. Could you please tell me is there anything else I need to add？
.SUBCKT INV_X1 VDD VSS A ZN
*.PININFO VDD:P VSS:G A:I ZN:O
*.EQN...
Dear all,
I extracted an inverter's HSPICE netlist with the write_spice_deck instruction from PT, and then used HSPICE and PT to perform delay analysis on the inverter. But for the propagation delay of the inverter, the result obtained by PT is much larger than that of HSPICE. I would like to...
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