Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
hi, szekit! u say worst case stability is at min output current and max output cap,
why the worst case stability is at these case? could u plz give a detailed commentate, thanks!
LDO stability
To give attention to the loading current range, Rc and Cc must be chosed suitably, but it always could not fit all current value , the phase margin could not good at some case
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.