Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Recent content by twotoo

  1. T

    Tool that generates layout from Spice netlist or Verilog code

    cadence encounter generate layout from synthesis ...Using the standard layout cell to set up your project may be a good approach since it's too simple to implement.
  2. T

    How to Simulation the noise of OP_AMP

    ye~~~ I have the same question~~~

Part and Inventory Search

Back
Top