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I would like to OR more than two signals.
I read that writing:
out <= in1 OR in2 OR in3 OR in4 OR in5;
or
FOR i IN range LOOP
out := out OR in(i);
END LOOP;
might create a cascaded structure like:
(.|.)|.)|.) instead of (.|.)|(.|.) or better (.|.|.|.)
How do I avoid this or can it not happen...
Plz describe what voltages you applied to what terminals (D,B,G,S) with the lowest voltage being 0V.
By reverse you mean that U_Drain < U_Source for an n-type FET ?
I guess for an n-Type the Gate usually has to be as positive as the most positive D, S Terminal, a more negative Bulk (perhaps...
Re: leading one detector
The named Altera source contains an example "onehot_to_bin". It works by using the period of the n-th bit in a counter to generate the OR pattern for the n-th result bit. This is done using two loops in a nested fashion. (See FvM's post #13)
I just don't know how I can...
I have found something: "Advanced Synthesis Cookbook" by Altera Corp. MNL-01017-6.0 July 2011 127 pages
cookbook.zip with examples
I even used the search term "cookbook" but the other terms must have been insufficient.
I am looking for resources (ebooks are not allowed) about basic digital circuits.
I do not know what to look for precisely. (or else I would not ask here but use go*gle)
There must be something like the top two dozen digital circuits that one can use to make up all the complex stuff. I am not...
Re: leading one detector
What FvM means is that you could use basic gates instead of processes.
I had the same idea as FvM (#11 11-02-11) and wrote this code (that has not been checked in any way) for a single byte:
ENTITY leadingone IS
PORT(ein : IN bit_vector(7 downto 0); aus : OUT...
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