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Can anybody help me design a clock fail detection cicuits without using delay lines.
I came across the attached circuit which can detect the clock failure of a high frequency clock used as clock1 with the help of a good low frequency clock named clock2.
My doubt is whether i can detect the...
I am really sorry for creating such a big confusion. I want to design a circuit to detect the attached waveform. I tried using two simultaneous counters and it is working fine. I wanted to know whether there is any other design so that i can do it in verilog hdl
i saw this method already in a paper so i wanted to replace it with any other better method (in terms of lesser area or power when synthesized), so that i can compare these two
Hi ads-ee, i got mixed up with the replies. i meant that i came across the approach that you described and i wanted to know whether there is any other method.
555 reply was for sunnyskyguy
Thank you so much. I came across this. Can you suggest me any other
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instead of using 555 can i develop it by any other means because i need modelsim simulation for that
Is there a possibility of replacing a up/down based frequency divider by a upcounter one with a rst signal
i.e, if a max count is given and an updown counter counts two and fro to max and to zero with a high frequency signal.
Instead of this can i use an up counter which counts to max and then...
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