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stiching capacitors
Hi
Its a four layer board and the layer stackup is like this
1. top
2. split ground plane
3. split power plane
4. bottom
where i have to route around 20-30 signals crossing split power plane.
is there any application notes or standard guide lines available for the...
hi
check for pcbenv directory and file env
edit env file and do the following
eg;
alias F4 "delete"
alias p "place manual refdes"
alias ~L "redisplay"
# ~ for control
or
open allegor pcb editor
on allegro command line do the follwing
alias p "place manual refdes"
--TuX
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