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Thank you for your explanations.
As I understood, each bank has different voltage inputs and each bank's inout pins got values according to voltage supply.
For example, If Bank0's supply voltage is 3.3 V, all of inout pins in this bank will be 3.3 V.
I will take into account DS162, UG381...
Hello;
I am designing an electronic card that includes FPGA (spartan 6 XC6SLX45 - 2CSG484C).
Is all inout pins of Spartan -6 3.3V ?
I checked Spartan 6 evulation board. Supply voltage bank have different input values. For example; some voltage inputs 1.2 V and some of them 3.3 V.
Is each...
I suspect state repeated start and ack state after i2c address reading. I send register enable on before read state and gets ack but still data line seems low.
My general algorihm like that, firstly write data to enable register then reading data.
START -> I2C ADDRESS + 0 -> ACK -> REGISTER...
My hardware description is true. On evaluation kit this circuit have already presented.
I removed ACK state (STATE_ACK3) after when I2C address sent, and I got more reasonable result.
Circuit gets ACK wait DATA transfer. I try to read green low byte from address 0x98, repeated start and read...
I drove SDA high z and 0, otherwise I can't communicate with device. I can get ACK in first pic which I sent device address and register address.
But I can't get proper data in second pic. Maybe there is something wrong in start condition.
Read status in states STATE_ADD_CALL2, RW2 and ACK3.
I...
Thank you very much for your suggestions and helps.
I revised again verilog code, and I can get ack when I sent both Device Address and Register Address.
Repeated start condition have been adapted into code, Outputs and verilog code below.
There's some mistakes when I sent second I2C...
I revised verilog code according to you said. I sent 1 byte and wait 1 bit ACK. But still can't get any data from slave.
Circuit have pull up resistors.
True I2C address = 0x39
I drove SDA high or high-z when wait ACK or data.
Evalkit sent by producer scope output:
Verilog implementation...
You're right, there is valid voltage level in real circuit. I tested change in ack and data bit as shown scope out. Blue lines in the test bench are drived HIGH in real circuit.
Is driving SDA HIGH-Z when we expect to get data incorrect ?
I've an evaluation kit and I'm implementing code on this:
Evaluation kit has already pull up resistor. I checked connections between FPGA and evalkit.
I'd revised verilog code and written I2C address into code. But there is no change in data, still can not get any value.
I tried to send...
Why I need use pull up resistor ? Input voltage of sensor is enough to communicate.
Is that necessary to get data in address ? I must point address, and I made it wrongly.
For instance in SDA line, I send address value to sensor as 0x98 but in scope outgoing address vallue seems different...
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