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Recent content by tulsi

  1. T

    vhdl code for CDR(clock and data recovery)

    Hi all, can any one help me to get vhdl code for CDR clock in receiver. have to recover clock and synchronise the data from 32 bit random data . data rate is of 100kbps for logic '1' and 12 kbps for logic'0'. please help me out from this problem. hope i will get some help from this site...
  2. T

    is it possible to write a hdl code for single error correction and double error detec

    hi, is it possible to write a hdl code for single error correction and double error detection. in transmitter . Please help me if any one know this.Or what are the different mechanism to do this. Thanks in Advance Tulsi
  3. T

    how to recover the clock in digital communication.what are the best way to do this

    thank you.. im using dpll and it contains edge detection and sampling method right. is there any vhdl code for clock recovery bec im new to vhdl and im finding lot difficulties in understatnding it. atleast give me logic. you can mail me at tulsi8788@gmail.com Thanks in advance
  4. T

    how to recover the clock in digital communication.what are the best way to do this

    for low speed 12kbps and for hi speed 100k bit per sec.
  5. T

    how DPll method is used for recovering clock and data synchronisation

    hi, how DPll method is used for recovering clock and data synchronisation in digital communication for 16 bit serial data. Thanks in advance tulsi
  6. T

    how to recover the clock in digital communication.what are the best way to do this

    thanks for your positive responses towards my threads. what are the different mechanism for clock recovery.can we use BER method. how to synchronise data and recover data at the receiver. which decoding technique is useful in digital communication,which can be implemt on fpga .
  7. T

    how to recover the clock in digital communication.what are the best way to do this

    i would like to thanks for your quick reply. even i suggested my madam to use pll but she said how u implement pll in digital communication as it is an analog pll .Is any other simple method to recover clock at the receiver in digital communication which can be implement on fpga.
  8. T

    how to recover the clock in digital communication.what are the best way to do this

    hi, how to do with 8B/10 B encoding ,can you explain little detail, and can we recover clock and data by edge detection( xor with delay).
  9. T

    how to recover the clock in digital communication.what are the best way to do this

    How to recover the clock from serial data(serial data coming from Rz encoder) to get original data in digital communication. What are the different methods to do this. Please help me. Thanks in advance
  10. T

    can anybody help me to draw a state machine for fifo

    Thank u ... this code helped me to understand n to draw ---------- Post added at 07:40 ---------- Previous post was at 07:36 ---------- its not that i dint tried .... i have tried it and drawn diagram also but i want to know when the fifo controller sends Fifo empty and fifo half full signal...
  11. T

    explain BILBO shift right register and use one xor to generate parity

    hi, explain BILBO shift right register and use one xor to generate parity or after shifting the data from left to right using several d flipfop , how to check for parity by using single xor.
  12. T

    can anybody help me to draw a state machine for fifo

    Hi, pls help me to draw a state machine for fifo with all states and their description . pls help me its urgent Thanks
  13. T

    state diagram for bit counter

    hi, Can any body help me to darw a state machine diagram for bit counter and 32bit shift register . Wher bit counter is connected to shift register and shift register get a data from fifo
  14. T

    what are the components of rz encoder

    hi, what are the internal and external components of rz encoder. Thank u.
  15. T

    what are the input and output pin description to rz encoder using mux

    Hi, what are the input and output pin description to rz encoder using mux in arinc 429 protocol. Pls reply to my question. Thanks
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