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You guys are correct. I did that for a short moment for some reason. It was already in the late hours so I did not pay proper attention. Going to try it in the morning.
Implementation of SIGNAL -> FIR FILTER -> DAC;
Works fine in simulation, is matlab generated filter but because of the following warning
"WARNING:Xst:1290 - Hierarchical block <U0> is unconnected in block <DSB_TOP>. It will be removed from the design."
And I can't seem to figure out what is...
Everybody , thank you for all the help and tips, greatly appreciated !
This is what I have now. going to work on the DAC side and see how it works.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
entity ADC is
port(
clk_inadc : in STD_LOGIC;
clk_adc : out...
Why would it only work when it is an actual 48kHz clock and not one that is derived from the main clock? It is not like if there is a separate clock input that that one and the main clock will be exactly synchronous AFAIK.
I fully understand now. But won't this FIFO with independent clocks do the same as the solution mentioned above ?
(assuming slave = adc running at 48K , Master = filter = running at 25M)
Thank you for the response. My question now is won't the clock difference between the clk_adc and filter_clk mess things up? or is this wrong thinking from my side.
If that is the case that process would have to run on the filter clk (25M) correct ?
Thank you for that information, I have registered and downloaded the full specification.
If I understand correctly it should be like this:
my spartan6 only has 16 DSP slices, my filter is 51 coefficients and since the filter only seems to be able to do everything in parallel it has to run on...
Hello,
I have made my clk div code, adc code and DAC code and generated the FIR filter using XILINX's FIR COMPILER 6.3 for my spartan 6 FPGA.
My filter is running on 25MHz , adc and dac on 48kHz.
Now I have the following questions regarding connecting it to the AXI-4 FIR IP block;
1. Since...
Yes, that is what I made. But that seems the wrong approach now. I should just make it accept my raw (decimal) ADC value which is up to 4096 so 12Q0 or 13Q0 (or something like that).
Correct?
I generated HDL from matlab, trying to connect it to my VHDL adc / dac code.
I see that I have thought wrong, the whole conversion from binary to real / float is not needed. I should just make my fixed point input in matlab so that I can just put the raw binary value in there.
As in 12Q4 for...
I must be really stupid because I can't seem to find the answer online after a long time searching.
My system consists of ADC -> Decimation filter (matlab) -> DAC
I got the ADC , DAC , clkdiv all working with relative ease but I'm having troubles with a simple step.
The ADC / DAC is 12 bit ...
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