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You can search for "gate control" techniques for HV design.
But for power control applications, there should be special HV process for design.
Otherwise, using 1.8V process to realize 36V ckts is not easy.
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For EX.
LDMOS in 1.8V process might be a good choice for HV...
I do not find any paper or reference talk about this issue on LDO pass element.
Does anyone can give me reference?
This paper discuss TDDB on nanoscale CMOS reliability, especially on startup and standby conditions.(on page 1696 and 1697)
It seems pass element in LDO will encounter this problem...
If I use the architecture as pass element (as the figure below), cascoding a core PMOS under pass element, better PSR is surely achieved.
But can it get rid of the risk of GOI damage?
In deep-submicrometer technologies,
the thickness of gate oxide has been scaled down to increase speed.
In the meanwhile, the breakdown voltage of gate to drain or source also decrease.
Take LDO circuits for example, in shutdown mode, Vout will discharge to 0V,
but the PMOS pass element's gate...
Someone suggest me size finger=2 as unit block for MOS' dimension in 65nm technology, especially for current mirror and differential pair.
It's based on his company's experience, so he doesn't know the reason.
Does any reference can support this concept ?
Input voltage source is set as DC=0.6V, ac=1V.
I use hspiceD to simulate the same ckt, and
I find that the hspcieD pz analysis results can match with Bode's plot create by Spectre.
The situstion is the same as the problem below:
https://www.edaboard.com/threads/48269/
I have the problem, too.
My Spectre pz analysis results doesn't match Bode's plot.
My simulation is for LDO circuits.
Poles (Hz)
Real Imaginary Qfactor
Pole1 -3.18776e-02 0.00000e+00 5.00000e-01
Zeros (Hz)...
Spectre can't be just declared the outputs, and it enforce me to declare input voltage or current source.
Then I replace the iprobe with a large inductor in order to break the feedback loop at ac analysis.
But the pz results still can't match Bode plot.
When output voltage is declared, Positive...
Dear all:
When I simulate a LDO circuit by Spectre, I find a dominat pole at low frequency on Bode plot.
But in pz analysis of Spectre, there's no pole at low frequency.
Why the two results between Bode plot and pz analysis are quite different?
Does the miller cap compensation will effect the...
Dear all:
I want to design a LDO at loading from 0 ~150mA.
But I find it difficult to compensate the LDO at light load.
Is there any technique for LDO compensation at light load?
I have an inl & dnl simulation code by Matlab as the attachment, but I think this file isn't effective. Because I have to input sine and ramp signal to get the performance of dynamic (fft) and static (inl & dnl) respectively.
By using LA (logic analyzer) in testing ADC, we just need to...
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