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Recent content by TrickyDicky

  1. T

    Error when trying to refer to components generated by "for .. generate" loop VHDL

    The formal vhdl term is "external name". It was added with vhdl 2008 and I don't think it it's supported by any synthesis tools.
  2. T

    Declaration of a constant that chooses among other constants of different sizes in vhdl

    Whats wrong with the code you already have? As far as I can see, you just need to change the assignment of c_mult to VHDL 2008 friendly code (ie. an initialisation function, that can mostly be a copty/paste of what is already there). 1675433310 To be honest though - I think I agree with barry -...
  3. T

    Declaration of a constant that chooses among other constants of different sizes in vhdl

    So Prime Pro Has more VHDL 2019 support that I have seen listed. (I dont work with intel parts) The documentation only lists Conditional Analysis and VHDL interfaces from VHDL 2019 as supported...
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    Declaration of a constant that chooses among other constants of different sizes in vhdl

    @rafimiet Im not fully convinced by your arguments: You cant have synthesised as when..else is not available as part of a initial value assignment until VHDL 2019, and I am not aware of any synth tool that provide VHDL 2019 support of this feature. (Maybe you did it in a function, which has...
  5. T

    How do I interpret "if" statement in different always_comb situations ?

    Thats not an always_ff block, its an always block using i_c and i_r as enable signals. Hence you are creating transparent latches.
  6. T

    Why doesn't shared variable drive output port in VHDL when using concurrent assignment of shared variable to signal?

    Direct from VHDL 2008 LRM: architecture_body ::= architecture identifier of entity_name is architecture_declarative_part begin architecture_statement_part end [ architecture ] [ architecture_simple_name ] ;
  7. T

    Why doesn't shared variable drive output port in VHDL when using concurrent assignment of shared variable to signal?

    X_i is not a signal, hence it has no 'events to trigger the process infered by the one line assignment. You basically have this: process begin o_x <= x_i; wait; end process; 1670975341 Wrong. Both architecturearχtecture and arch_name are optional. So you can do any of the...
  8. T

    How does "include" work in Verilog?

    include basically does a copy+paste of one file into another. Try it yourself. Instead of using `include, try copy/pasting the other file into the one you're working on and see if it still compiles or makes sense.
  9. T

    Varying Verilog code simulation results in "Xilinx Vivado" compared to "Xilinx ISE"

    Another point to note - ISE has not received any updates for 8 years. The vivado version you are using is 3 years old, but you could be using a newer version. Xilinx simulators have never had a good reputation.
  10. T

    Float pkg is not working in VHDL

    Yes, unfortunately you need to generate a core from the catalog, and then instantiate it in your VHDL code.
  11. T

    Float pkg is not working in VHDL

    You don't specify what tool you are using or where you are seeing the error. Have you set the tool up in vhdl 2008 mode? Float pkg is only available from 2008. I do not recommend using float pkg for synthesis code as it does not have any pipelining. Use available ip cores instead
  12. T

    [SOLVED] Xilinx IP Core with native data in and AXI bus data out

    @ads-ee AXI4 FUll also requires the use of Address and data buses. The OP specified no information about how or where the data is transfered. AXIS has byte enable signalling as well as packet transfers (or bursts). So my question is still valid - do you want to use AXIS or a memory type transfer...
  13. T

    [SOLVED] Xilinx IP Core with native data in and AXI bus data out

    Axi streaming or axi4 full or lite?
  14. T

    How to declare a non input use in vhdl?

    You must assign all bits from the same array in a port map before assigning another bus. So assign all of a before you assign b.
  15. T

    10533 VHDL wait statement error

    Modelsim is a code simulator, and will simulate exactly what you write. There is a lot of code that is not synthesisable but is perfectly valid and useful for simulation. Like wait statements. Vhdl was originally created as a modeling language. It was later that tools were created to...
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