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Hi rongo024,
Thanks for your reply. 555 timer just generate a wider pulse from a pulse-trigger. My problem is that I need to detect a 50ms pulse. The attachment is a logic diagram. Thanks.
Hi all,
I need to design a circuit in power management IC to detect power key action: in power off state, when detect >50ms High pulse on power key, PMIC should enable system. (in this case, 1Hz clock is always available)
My question is: if no signal from host device (CPU) can be used, how to...
Hi all,
As attachment, the class-AB driver output is audio signal (20~20KHz) and has 1~10mV DC offset. Is there any method or close-loop DC offset cancellation circuit to eliminated it? Can the so-called servo circuit solve this problem in this case? Thanks in advance.
Regards
Hi all,
I want to use ADiT to do fast-spice simulation and need call a Verilog-A in it. Would you please tell me how to call Verilog-A in ADiT? I can not find it in the user manual. Thanks in advance.
Regards,
Trashbox
Hi all,
#1.
I need to add a negative voltage on the PCB for my test chip, the average output current is about 100mA through this voltage. Except the charge pump chip, how can I realize a negative voltage with simple method on PCB?
#2.
I also need a big size mosfet (power transistor?) with...
esd protection how it works
Hi all,
As the attachment, the left-side is a general vdd/vss ESD protection circuit. How the M1/M2 works when it is under Positive-mode ESD test as described in the right-side? Thanks in advance!
--Trashbox
Yes.The spec. is RTC power <3uA
Suppose the oscillation waveform peak-peak value is 3v, the current through this feedback resistor is about 3V/15e6 ohm=0.2uA
I simulated it as following:
VDD=3.0v
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MOS in series
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VSS=0v
and probe the current through MOS so that the...
When I simulate real-time clock crystal's open-loop with ac, there are two cases as attachment:
1)The BLUE result, it uses a ~15meg resisitor as the feedback for setting inverter's operating point. This result is what I needed.
2)The PINK result. it uses several switches in series(a switch is a...
rtc capacitor
Thank FvM very much!
Yes. Because it's the first time for me to design RTC and no info about the parasitic packaging capacitors, I have to add options in this test chip.
Yes. I'm afraid even the crystal is very good, my circuit's non-ideal factors such as packaging capacitor...
real time clock crystal capacitor
Hi all,
Regards to the 32.768KHz crystall oscillation circuit design for Real-time clock(RTC), some papers use tuning capacitors for frequency trimming such as the red capacitor Cx in the attachment. However, 32.768KHz crystal generally has a very small...
Hi FvM!
Thanks for your reply. If no RESET, how can you set the initial value? Just as you said, if no initial value is assigned, the output stays at "X" state permanently.
Regards,
Trashbox
I need to divide a clock(freq=200KHz, duty cycle is 40~60%) by 4 without reset signal. This clock is IN at the attachment and the desired output is OUT at the attachment.
Many counter need a RESET control signal. If no RESET is available, How can I realize such a function? Thanks!
Best regards...
Hi all,
Is there any papers about high power supply rejection (>50dB@10KHz), large output current (>300mA), area- and power- efficient low drop-out regulator design?
I've read some Rincon-Mora's papers from Georgia Tech and need more materials about this area. Thanks very much!
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