Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
NMOS need +Vt for on,when gate voltage is 1(Vdd) and source voltage applied is 0, than Vgs(GATE to SOURCE) become Vg-Vs=Vdd-0=Vdd which is greater than Vt so it allow strong 0 and output is 0.If source voltage applied is 1(Vdd),than Vgs=Vg-Vs=Vdd-Vdd=0 so NMOS not allow 1 so NOMS act as open...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
