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K-J thank you for reply. Actually I wrote it with "begin" but the program gave me more than one error about my variable "converted" I defined this variable but It says "undefined symbol" and "unexpected variable" for all the lines which have "converted"
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_ARITH.all;
use IEEE.std_logic_UNSIGNED.all;
use ieee.numeric_std.all;
entity sevenseg is
port ( sw: in std_logic_vector (7 downto 0);
clk: in std_logic;
ssegon: out std_logic_vector(3 downto 0);
sseg: out std_logic_vector (0 to...
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