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Recent content by topza

  1. T

    How to do post-sim in modelsim with quartusII?

    i can remember only this compile your netlist+altera library+delay file you can find altera library under quartus directory(?) delay file generated by quartus. for your reference.
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    HDL Entry vs. Schematic Entry Tool?

    verilog i use verilog. i think it is easier to learn and grasp than VHDL
  3. T

    any guideline about design reuse?

    xilinx reuse filed guide may be you can find it on www.xilinx.com. it describes a set of guidelines to facilitate design reuse on System on a programmable -chip.
  4. T

    clock-tree-guideline from ATMEL

    clock-tree-guideline from ATMEL
  5. T

    Is there any reference on IP design

    i wanna extract some reusable modules from my ASIC project. i hope they can meet the needs of IP. but i have no experience on IP design and donot know the requirement. i wish you can share your experience and refrences to me :)
  6. T

    code resuse in verification

    METHODOLOGY AND CODE REUSE IN THE VERIFICATION OF TELECOMMUNICATION SOCs
  7. T

    How to use pipe line design to speed up the clock

    pipe line (ppt) use pipe line design to speed up the clock
  8. T

    Open Core Protocol Specification 1.0

    it is good for me :o Do you want to thank someone who uploaded 10 months ago a publicly available file which is NOT available on elektroda anymore ?? Really strange :wink: 1 WARNING SENT ! (-5 posts and points decrease )

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