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Recent content by tooh83

  1. T

    Difference between locally & globally static expressions

    Hi all; I can't understand the difference between locally & globally static expressions in vhdl . LRM is not clear for me , can anyone provide good explanation/examples to illustrate this Thanks
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    best way to learn functional verification ?

    hi all I need to know the best way to learn functional verification . Through web browsing i reached this conclusion (correct me if i am wrong) functional verification has different technologies 1]Assertion based verification : where u write assertions into ur vhdl/verilog code using...
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    Manchester encoder /decoder

    manchester encoder vhdl hi vintujose Chapter 10 in Pong P.Chu book "RTL hardware design using vhdl" contains a manchester encoding circuit vhdl code . u can find the book here on
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    how to calculate the setup and hold time ,thanks

    digital setup hold time calculation I think 1) C 2) D
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    How to import schematic for PCB layouting?

    Re: Cadence Question hi laiza I hope these presentations are useful
  6. T

    Best book to learn Verilog?

    best book to learn verilog check this topic on edaboard
  7. T

    Introductory materials about floorplanning

    Re: floorplanning i need to know at first what is floorplanning ? how to floorplan ? floorplanning algorithms ? a step-by-step floorplanning example and plz in english
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    Introductory materials about floorplanning

    hi , everyone I want to learn floorplanning . can anyone give me a good introductory floorplanning material . thanx in advance
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    vlsi recruitment websites in Egypt ?

    Well actually I want to work as a digital IC designer (ASIC/FPGA) but the problem is that I'm an 2006 graduate and I have no work experience at all (thanx to army) . I'm located in Nasr City , Cairo .
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    vlsi recruitment websites in Egypt ?

    hi all I need help regarding vlsi recruitment websites in Egypt . I have just completed my military service and I ' m currently looking for a job in this field
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    parallel port clock pin

    parallel port interfacing bibin john rapidshare hi i need to know if there is a pin on parallel port on which i can c the parallel port clock when writing or reading data from port .. the parallel port is in ECP mode .. thanx in advance
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    Vhdl question about process(enable) syntax

    Re: Vhdl questions 1) here is a decoder code in which i m using enable and in the attached figure as u can c it is implemented as a register with enable as a clock : code : -------- library ieee; use ieee.std_logic_1164.all; entity decoder is port ( enable : in std_logic ; data : in...
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    Vhdl question about process(enable) syntax

    Vhdl questions hi i have two question 1 -when i write the following lines process(enable) begin if (enable = '0') then do sth.. it is hardware implemented as a register with enable as a clock input but i dont want the enable to be a clock 2 - any one knows how to simulate INOUT pins in...
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    Code for assigning internal clock of EP1C3 FPGA

    hi all i m using EP1C3 FPGA, -8 speed grade , i want to assign its internal clock as the input clk to a 4-bit counter whose VHDL code is as shown entity counter is port ( enable,clk : in std_logic; count : out std_logic_vector(3 downto 0) ); end counter...
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    VHDL command for: if (signal changes) then do something

    hi i need to know if there is a command in vhdl which can do the following : if (signal changes) then do sth.. and if the answer is no then how can i do it ? thnx in advance
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