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Thanks yuvan.
What I meant was divide Lx by 100 while times Cx by 100, so the center freq is still kept the same but the new Q (de-Q) will be smaller due to the bigger Cx.
Also, how do I calculate the steady state current for the Gm stage? Thanks.
Hi Guys,
I de-Q'd the crystal oscillator by adjusting the values of Cx and Lx to give the right w0, my transient simulation is dramatically faster but why the f0 is shifted a bit to ~33.5KHz? Thanks.
tommydidi
Re: Ask forPg. 156 ~ 161 from the book "Sub-threshold Design for Ultra Low-Power Syst
Hi erikl,
Thank you so much for your help. Can't send you private mail due to your configurations. Other ways to reach you? Thanks.
tommydidi
Ask forPg. 156 ~ 161 from the book "Sub-threshold Design for Ultra Low-Power Systems"
Hi Guys,
Is anybody nice enough scanning some pages off the book "Sub-threshold Design for Ultra Low-Power Systems" by Alice Wang, Benton H. Calhoun & Anantha P. Chandrakasan for me? I need the contents from...
Hi Guys,
I always heard of the nwell capacitor is more tend to leak than poly cap or MIM cap, can't find any document so I can understand it though. Can anybody explain this to me or point me a direction so I can find something to read? Thanks for the help.
Guys,
I sometimes saw a nmos-connected diode in series with a pmos-connected diode. The circuit is somewhat like the one I put in the attachment. The Vg of M1 is regulated through other circuit, so the current through it goes up and down. I don't quite understand the purpose of having two...
Guys,
I am design a NMOS LDO. Now I have finished the charge pump (switched cap) and working on the err amp. The questions I have for you guys are:
1. Do I need a buffer stage for the err amp?
2. How can I simulate the whole loop stability? Not sure how to model the charge pump, any idea...
Thank you guys. Here is the full circuit w/o the bias generator part. I donot want to increase the CLoad cause I have the area constrain. Basically I need a zero at some high frequencies to lift the phase up. So anyway of kicking in a zero?
Hi dedalus,
Thank you for your post. Actually the drain of the pmos input stage IS (not ARE) connected to the nodes between drains and sources of the BOTTOM nmos cascode. The first stage has its own current mirror load. It's two stages for sure.
Hi there,
I am designing a two stage opamp (drives a capacitive load) and looking for a way to compensate it. The first stage is a typical pmos input and the second is a cascode one, please see the picture below (only shows the second stage). The "vb1, vb2 and vb3" are bias voltages generated...
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