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Thank you for the reply.
So I think when I instantiate a divider, I still need to use the generated_clock to define the relationship bwtween the input and output clocks of that divider. The "gate delay" is the the component delay inside the divider, e.g., the delays of combinational gates and...
About geenrated clocks
Hi everyone,
I have some questions about the geenrated clocks.
When a divider/multiplier is used to generate an output clock clk_out according to the input clock clk_in, we need to define the clk_out as a generated clock sourced from clk_in. In the synthesis:
1) Do we...
Hi everyone,
I have some questions about generated clocks.
When a divider/multiplier is used to generate a clk_out accoring to the input clk_in, then we define clk_out as a generated clock from clk_in. In the synthesis:
1) Do we need to set the generated clk_out as ideal or dont_touch?
2)...
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