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Recent content by tok47

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    IBIS model generation using SILICONSMART

    Anyone creating IBIS model using SILICONSMART ?
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    [ OPPSTAR @ MALAYSIA ] : Job Openings

    Hi ALL, The company currently is expanding and welcoming talents to join. Please go to the website and submit your resume. **broken link removed** Thanks.
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    [ Job @ Malaysia ] : Physical Design Engineer, Design Validation Engineer, RF Wireless system architect and designers.

    Hi, My company is looking for professionals to fill up several positions. Please PM me.
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    Silicon Characterization for Std. Cell Library

    Hi ALL, Do anyone familiar with the flow / processes to characterize std cell library at silicon level? Rdgs YY 1614151916 i want to understand the flow.... (1) normally how long it will take. (2) what are the tests need to be done
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    Standard Cells Library Silicon Validation

    Hi, Is there anyone here know the method? i need some guidance on this. Rdgs YY
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    PMV48XP Hspice model

    There was no any nsub value in the lib file. It use Gamma and Phi to determine the nsub i am running a pspice model with hspice tool. Is it workable? I think the limit of nsub is different for these 2 different tools.
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    PMV48XP Hspice model

    Hi ALL,, I am using the STANDARD MOSFET from NXP semiconductor. They provide a Spice lib in their website. **broken link removed** I plug in the model in my HSpice simulation. I did manually edit the Spice lib file to fit in for HSpice simulation. But, i have encounter the problem below...
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    Calculate the resistance of metal layer

    Hi ALL, I had a metal layer of bus signal which i wish to calculate the effective resistance of this layer. Please see the attachment file for the layout. Can i just calculate the whole rectangle and minus the the empty space to get the effective resistance? will it be accurate? Thanks...
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    verilog syntax error

    Hi ALL, I having a verilog compilation error. Need help adn guidance. I have a instance connected as below, USB_A0 U1 ( .PLLDIVM(1'b0), .PLLDIVK[1](1'b0), ); I have a compilation error : Error-[SE] Syntax error token is '[' Can I know how to solve this? Thanks. Rdgs YY
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    verilog strength coding

    then, how about bufif1 (weak0,weak1) G1 (A11,1'b0,DATAR); bufif1 (weak1,weak0) G2 (A11,1'b0,DATAR); any different for these 2?
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    verilog strength coding

    Hi all, Will these 2 giving a same output? bufif1 (weak0,weak1) G1 (A11,1'b0,DATAR); bufif1 (weak0,weak1) G2 (A11,1'b0,DATAR);
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    rise_transition in .lib file

    Halo ALL, I am trying to cross match the lib file data with simulation output. In lib file, rise_transition ("del_1_6_6") { index_1("0.24, 0.48, 0.96, 1.2, 2.4, 4.8"); index_2("1.86655, 6.86655, 11.8665, 21.8665, 36.8665, 51.8665")...
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    Request PCI-Express 2.0 Timing Library (.lib)

    To all, I am looking for PCI-Express 2.0 timing library. Please send me link that i can download it. Or please send me here if you have. Thanks
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    Request PCIe Timing Library

    Hi ALL, Can I know where i can get a .lib file for PCIe? Thanks. Rdgs YY
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    Need 30MHz crystal model for simulation of [Oscillator Pad]

    I come across this site yesterday as well. Thanks.
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