Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
its not really strange. its to do with power consumption.
at this voltage level you are talking consumable electronics where ever drop of current counts. ... longer battery life
why send 2.6volts or whatever to a fpga when it might only be performing useful tasks for 60% of the time.
for 30%...
well I imagine the vrm module 'will' be altering the vcco voltage and the voltage of the internal rails of the fpga.
thats why I ask if its possible to do this.
I have been given contradicting answers to this and i am quite confused...?
I was thinking a watchdog timer could be used to monitor...
hi guys
Is it possible to use a spartan 2 to control the VID levels of a vrm module? and also perform calculations on a different block inside the fpga?
I would be looking for have some control of the power coming into the fpga - (Vcco)
thanks
hi lads and happy holidays
I am trying to implement a routine, basic code on a fpga with verilog.
this will simply perform some calculations, adc/math operands etc to alter the supply voltage.
I am doing this to simply have control over the power usage of the fpga.
also I would like to have...
hi Guys
I have a test bench written for my 16 bit ALU and this is what my simulation gives me, is this correct even.?
I have just used one operand at first (A + B), to see if its ok.
The signals are a,b inputs, c is output c_nx is also an output
thanks for the help :)
hello
Yes, I got my code working. well i got it synthised on xilinx ise
I need to create a test bench for it now and having problems.
an someone help me with the test bench for this please? I ran it on multi sim and got an error to do with the c bit being the incorrect size and a few other...
well,
I have been over complicating my code way too much. I dont need any carry, sum flags or regs.
Making it too complicated for my own sake. The output is a 16 bit word, plus 1 bit for the 2s compliment bit.
[s][msb].................[lsb]
I have attached a block diag of my design.
I have also used a updated block of the final product as the original misses out on carry inputs etc.
I changed my code also, slightly regarding the port declarations.
ha,
thats correct...!
c[s + 15:0] is the output
where s is the 2 signed compliment output word
so that can be amended to my code.
I am not sure what I do with this S, and how I declare it ?
its a > 'reg signed s' I would think ?
1 bit word? is this declared just as in output reg..?
s is to signify a signed o/p i presume...
in verilog all declarations are unsigned for default, so you need to tell if they are signed,
so i had to say signed for the output to let it know.
how I deal with regs and storage is another thing, and If i can implement this in one always loop....
Hi ya,
thanks for the help, yes I understand. I was wondering about the extra 'bit' for the carry operation...:|
the two inputs a,b are 'unsigned'
the output, c is 'signed'. [s + 15:0]
does that mean the output is 17 bits?
I have included the ov term for overflow in the declarations.
I...
greetings all,
can anyone with verilog skills help me implement this ALU, I wish to firstly get the basic operations functioning before i move onto the more difficult tasks.
It wont compile, I am getting an error with the endmodule part? also do I need another reg to store the overflow bit and...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
