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Recent content by tj.diego

  1. T

    What's your first microcontroller unit?

    ATmega8535
  2. T

    AVR ASM SPM implementation

    Hi guys, i have some trouble to get work some SPM instruction and i can't to figure out what's wrong with it. the data are sent through the USART interface and when a line of the intel hex format are sent the page buffer should be written into the flash memory in the application section, but...
  3. T

    matrix assignment and loop in testbench questions

    Thanks a lot for you answer!!! 1) indeed it works, i did a little stupid mistake! 2) ok i'll try some alternative way to solve it and i'll post it! :9
  4. T

    matrix assignment and loop in testbench questions

    Hi to all! :) i have two doubts/problem about matrix: 1) if i have a matrix type declared as: package matrici is type matrixrow is array (4 downto 0) of std_logic_vector(8 downto 0); type matrix is array (4 downto 0) of matrixrow; end matrici; and i want to assign manually...
  5. T

    vhdl testbench strange problem with a ripple carry select

    before the loop i set the signal BB9 to 0, so in the first iteration just AA9 should changes, but this instruction BB)<="000000000" seem to be useless! what do you suggest to do all the combinations?! ---------- Post added at 16:31 ---------- Previous post was at 16:26 ----------...
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    vhdl testbench strange problem with a ripple carry select

    the input B is driven in the testbench from the signal BB9, if i use direct assignment like BB9<="000010000"; it works, but if i use the for loop to do all the combinations, it seem to be floating...it doesn't have any sense for me...i checked the code several time but i can't understand!
  7. T

    vhdl testbench strange problem with a ripple carry select

    i tried it, but it didin't solve the problem! i still have the output and the B input equal to "UUUUUUUUU"!!! thanks all for join the thread
  8. T

    Fgpa based image processing

    I'm not using any FPGA, but I am simulating some tracks for image processing as sad and wavelet, if you are interested I can get the material!
  9. T

    how to make three function parallel shifter in vhdl

    I hope it can help Overview **broken link removed**
  10. T

    simple verilog doubt by verilog beginner

    I'm not sure I understood, but a NOT gate could be for you!
  11. T

    vhdl testbench strange problem with a ripple carry select

    [SOLVED] vhdl testbench strange problem with a ripple carry select Hi all, i have a strange problem with a testbench, if i define the inputs separately i have no problem,but if i use two for loops to have more combinations easly the second input BB9 is equal to "UUUUUUUUUU" like the output...
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    Uninitialized out port

    i did it, but this time didn't work, btw thanks a lot for your advices!!! :)
  13. T

    Uninitialized out port

    i expected something like "the port s(8 downto 0) doesn't exist" btw i'm learning how the compiler talk to me! :)
  14. T

    Uninitialized out port

    what a shame....i'm really sorry, i checked the code, but i didn't saw the error! btw i thought that this kind of error are reported from the compiler!!! so i was looking for some more important error!!! thanks again!
  15. T

    port mapping and signals in a loop

    yes you was right too, but his answer was more helpful! :)
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