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Re: Question about Flash ADC - help needed
I have a littel problem,i want to do the same analysis as in the attachment..but to da that I need a 5-bit ideal DAC.
Someone has a verilog-A code of a 5 bit ideal DAC?
Re: Question about Flash ADC
Thanks Joannes for your replies.
Now I show you my simulations:
InPreamplifier shows the differential oputput of the T/H circuit and Vref+ - Vref-
OutComp2Differential shows the output of the second stage comparator. It's the same of (vop_c10 -von_c10)...
Re: Question about Flash ADC
Really the simulations show the difference between Vop_c10 and Von_c10. I mean, (vop_c10 - von_c10) and not the single value of vop_c10 and von_c10 which are not represented.
Maybe I found a solution: the single output vop_c10 drives two stage of inverters to...
Re: Question about Flash ADC
Thanks for help.
To be more detailed I show you this file. It's a power point presentation of the previous pdf file. At the end there are the outputs of the preamplifier,first comparator and second comparator. I have obtained the same results and as you can see the...
Re: Question about Flash ADC
do you mean I have to use cml logic for the encoder because it's more suitable at high speed and also because the input is differential?
Re: Question about Flash ADC
sorry I didn't understand..can you explain me in more details?
In order to drive the encoder it's correct to do this operation: (Vout+ - Vout-), where Vout+ and Vout- are the outputs of the second stage comparator?
Reading the pdf file seems that it's the right...
I'm designing a full Flash ADC , my project is similar to that one presented in "adc 4 bit.pdf".
I have simulated all the stages and I obtained the same results..Now the problem is: Which are the inputs of the ENCODER?
I mean,if you look to the pdf file,in the first page,section II.System...
CML comparator
Hello everyone.
I need to design this circuit for a full flash ADC 4 GS/s in 65nm CMOS.
There are some rules to do that? for example, how can I choose W, I bias and Rload for this circuit?
please, I need a big help.
circuit:
sorry but I have other questions:
In this scheme what does mean Vin+ and vin-?
Can you explain me with an example?
i'm simulating the Track and Hold with pspice student,how can I calculate the HD3 and SNR with Pspice?
thanks all
ok, but if the wave doesn't have negative value,I have to use onlly Vref?
in the case the wave has this form, how can I choose Vref+ and Vref-?
Which is the value of 1 LSB if the resolution is 5 bit?
Hi all,
I'm designing a full flash adc,5 bit, 4 GS/s.
I have a big doubt about the choise of Vref. in many papers i saw that there are Vref+ and Vref-, why?
for example if the input is a sinewave Asin(2*pi*fin*t) with A=1V, power supply is 1.2 V, How can i choose Vref+ and Vref-?
In this...
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