Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
ddr2 timing question
I am doing a ddr2 sdram controller now.
how can I make the data written to the ddr2 sdram change every one half clock with its changing 90 degree before the dqs edge(just use verilog)?
I will do a ddr sdram controller design,but i dnt know how to capture the data at both pos and neg edge of system clock(because it is not recommanded to use both pos and neg clk in verilog)
could anybody who has this experience help me?
dear nand gates
thank you
i v thought about your idea before,but my teacher asked me to time the absolute time by asyncronous circuit without clk
for our chip may upgrade frequenecy (with shorter period)in the future and the no. of clocks cycles may not be enough?
do u hav any new good...
Re: Random No. generator
i have done this work recently
i recommended u to use clock contronlled generator(a type of nonlinear feedback shift registers)to get you random no.
as title,
when my memory control model does a read operation to eeprom ,according to the spec of eeprom,after the chip select signal and output signal is activated ,i have to wait for a time of 200ns until i can fetch the wanted data from the data bus.
Now,how can i wait for/time this...
the key difference is that:
if you have any data in a page of flash to be reserved when you do a new data write within the same page but different address ,you have to read the old data first ,then write back with the new data to be writen together.
but to eeprom ,you do not have to do this.
as title,
when my memory control model does a read operation to eeprom ,according to the spec of eeprom,after the chip select signal and output signal is activated ,i have to wait for a time of 200ns until i can fetch the wanted data from the data bus.
Now,how can i wait for/time this absolute...
i am doing a mmu design in a soc chip while the mmu manage the reading from/writing to Rom or Ram or EEprom
for i know little about the work scheme on EEprom,i want to learn about how to erase/write/program the EEprom.
are these work done by software? If so,what need my mmu do while doing...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
