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The frequency is depend on process, design margin ,.. If your FPGA board signoff @20Mhz , there are no reason you increase @30Mhz if you dont want to face with setup timing violation ,..
Tiep Ngo
It means your FF.Q expected value 0 after unload (shift out the data to the scan chain) .
I can explain more about it :
Q 000 - 100 - 000
[shift in ] - [capture ] - [shift out]
Tiep Ngo
That's right, it just a dataset , you need a framework for Machine Learning like lite tensorflow on the Pi but the learning time will slowd due to CPU core and dont have GPU support.
Tiep Ngo
For parallel pattern simulation, the values are forced in SI pin of FF's by the simulator and shift 1 cycle in your load/unload procedure.
What you should trace back is the clock , time it lanuch in the shift window and double check in your procedure
Tiep Ngo
1. If your design is HATPG you can check OCC ( On-chip Clock Control ) for more info. DFT will create 1 scan_clock for this purpose.
2. If your design is not HATPG, it meant you have 3 clock domains , and all 3 of them will be scan_clock . For your statement " 1 clock will be active at capture"...
Some item you need to check :
1. Clock period ? Is it correct with your SDF .
2. Simulator option is correct with your SDF ? -mindelay with min conner and -maxdelay with max conner ? Using notiming check in your script ?
3. Your STA don't cover your pattern ? For example : this path is...
First , I will cause the error when you are doing insertion (C1 violation) and stop your flow !
Second , if your flop cannot capture clock , how can it operate in functional mode ?
1. How to decide scan clock out of 4 clocks ?
-> We also have OCC only choose 1 clock ( scan clock ) from the TOP level.
2. I have read somewhere that only one clock needs to be active , Why it is so ?
-> You can check cross-clock domain ( which is unreal in most of functional function...
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