Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Recent content by thomasross20

  1. T

    Telescopic amplifier with different input and output CM's

    Hi all, I'm building a pipeline ADC... usually in the sampling phase, the amplifier is tied in unity-gain configuration. However, I'm using a fully-differential telescopic amplifier with output cmomon mode = 1.3V and input common mode = 0.9V... I've searched the literature but cannot find a...
  2. T

    Pipe-line ADC redundant bits

    Does a pipeline ADC using SC MDAC and ADSC even need a sample and hold at the input?
  3. T

    Pipe-line ADC redundant bits

    Hi, I'm new here.. I'm doing some work on pipelined ADCs and have just come across the whole 1.5bit stage/ digital error correction arena.. To be honest, I'm very confused!! Reading the above didn't really help, sorry! So there are 3 ranges.. -Vr to -Vr/4, -Vr/4 to Vr/4, and Vr/4 to Vr. This...

Part and Inventory Search

Back
Top