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Recent content by ThisIsNotSam

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    DRC errors

    Yes! But you gotta make sure you design following the same rules. Check your Innovus/Virtuoso settings too!
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    DRC errors

    The process is M9_6X2Z, which means it has 9 metals, the first six are of the type X and the next two are of the type Z. Most likely you are designing with the wrong stack. The most popular stack for TSMC 65 is 6X1Z1U, just so you know, as it is used in MPWs quite often. In any case, you gotta...
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    How to load time lib data in cts of innovus

    Then your clock division becomes the prime suspect. How are you doing it? A mix of RTL and SDC commands?
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    MemoryCompiler‘s SRAM LVS mismatch?

    Most likely you are missing some LVS configuration. Try to make a design that contains only a single instance of the SRAM and make that one pass LVS. Then move to a larger design. SRAM's can be tricky for LVS because it struggles with bit arrays and their relative order. Say, it tries to match...
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    Nwell floating when doing ERC check

    check if your library provides dedicated endcap cells for top and bottom.
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    How to load time lib data in cts of innovus

    are you doing any ccopt_* configurations or just running ccopt_design?
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    [SOLVED] Power stripe violation near the macro boundary

    scripting is usually the way to go. declare a variable x and a variable x_offset. drop the stripes one by one, add x_offset to x, rinse and repeat. add some corner cases in the form of if (x near macro) then skip if (x near macro) then apply offset times 2
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    [SOLVED] Power stripe violation near the macro boundary

    moving the macro or moving the stripe are the obvious options.
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    How to load time lib data in cts of innovus

    this is unlikely to be a missing library, looks like clock tree was configured by hand and something is conflicting
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    question on power analysis, after synthesize the verilog RTL model

    In general, yes, you can trust the tools are giving you correct results given the conditions you set. Accuracy, however, at this level, is low. Numbers coming from physical synthesis are much more reliable than those from logic synthesis.
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    question on power analysis, after synthesize the verilog RTL model

    conceptually, you expect that more logic will consume more power. but more lines of code do not necessarily mean more logic. it might just be different logic, that maybe is optimized differently because of the changes you did.
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    innovus power IO cannot connect with power ring

    The bond cell can be placed in different ways. You can do it with relative floorplanning with respect to the IO cell underneath it. You can also use a special command for this, I forget the name but it is something like placeBond or place_bond and it will try to do it for you. In the end, the...
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    innovus power IO cannot connect with power ring

    Yes, open the GDSII files of the IO cells and you will see the metals I am talking about. Innovus does not represent them because it doesn't have to.
  14. T

    Adding another pair of VDD and VSS in ICC2

    you have to calculate how much power it draws and how to size the *entire* power grid accordingly. there is no notion of IO cell ratio to block size, generally. the power grid is likely shared between many blocks unless you have individual power islands.
  15. T

    innovus power IO cannot connect with power ring

    there is a wire, it is huge. it runs through the entire pad ring and is fully connected, truly forming a ring around your design. you can inspect the layout of the cells, you will see the pattern. there are rings for VDD VSS VDDPST and VSSPST in some cases.

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