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hi..
i am doing an asic project now...in that i have to design 4:6 decoder in vhdl...is that 4:6 decoder is there...could any one explain about this logic to write the code....
Thanks in advance
hi..
sir I'm the begineer of vlsi design...According to Diagram i attached here..
with respect to the propagation delay.ie the minimum/maximum time(t3-t2) for the input to propagate and influence the output. the prop delay is less than holdtime(t4-t2)...is that true sir..or else the diagram...
hi friends,
i'm having 1+yr Exp in RTL Design(VLSI),Could you please suggests me...where i can get job..and how to search...
where i can post my resume...
is that any recruitment's there ????
please inform......
Thanks in Adavance
Hi,
Friends ...i did a program in verilog...after simulating i got the waveform as shown below...i got the answer..but in between the output waveform...i got some spike like strip...whenever my input changes...
i want to know.for what reason this kind of spikes occurs...
is that any...
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