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Error appears in translate phase that signal clkin2 has multiple drivers although it doesnt , main clock signal enters a DCM which generates 2 clock singles 1 acts as a clock for my vhdl module and other act as a clock for microblaze , the clkin2 is the clock of microblaze and its telling me it...
In my project i have my own vhdl code and also i am using a microblaze , now i implemented my vhdl code next to microblaze in the same vhdl top file , now microblaze clock input is directly from oscillator pin which is a 200MHZ clock and for my vhdl code i need a 100MHZ clock , so how from my 1...
Thanks mrflibbldre for your reply but i have went through this sites and here are their problems :
**broken link removed** this website just posts a discussion with no tutorial or vhdl code present , and Spartan3A cant use CY7C68013A , as CY7C68013A is used to implement vhdl into fpga using...
**broken link removed** this site conatins no implementation or a tutorial of usb implementation , its just a discussion, btw i cant use usb on my spartan 3a the CY7C68013A is just used to implement vhdl code to fpga.
Thanks mrflibble for reply (and time spent) but its useless( no insult , as...
Well my problem stated when i had my vhdl code up and running on my Spartan-3a but needed to send and receive data from it to the pc,
I need my vhdl code , so i went for a microplaze structure , problem is I cant understand how will my vhdl code and microblaze co-exist at the same time because...
1st The IC CY7C68013A cannot be acessed through the vhdl( correct me if i am wrong) but did u see anyone tries to communicate with it from fpga side ?
2nd Microplaze cant coexist with other vhdl files simply because when you program the fpga you delete it first .(again correct me if i am wrong)...
the problem is not on the pc side , its on fpga side as there is no source for a ready made ethernet vhdl mac controller , so i will have to use microblaze to interface with ethernet port , but problem is when i program my microblaze on my fpga it deletes my fpga implementation so all i get is a...
After alot of searching i saw some desginers using LVDS although i still need to know what is it and how to connect it to the pc and make pc detect it ....
Yeah it would be easier to use RS-232 or Ethernet but here are their problems and correct me if i am wrong :
The maximum speed of RS-232 is 9600 bits/sec while i need at least 56MBps so the choice would be ethernet then , but problem with Ethernet is that a packet or 2 can be dropped and still...
ok my fpga is spartan 3a starter kit it comes with :
usb port
Ethernet port
rs232 port
Now my fpga generates an output of binary and i want to rcieve that output on my computer( through a program written with java)
I want the most UN-complicated solution by your experiment with this cases , i...
The model is a simplified model of a much bigger model , i simplified it in hopes to find the error,All i have after behavioral simulation is post-translate simulation which doesn't show where the error is ?
Simply if i know why the timing error appears although everything in my code works at...
timing analysis says it can run at 180 MHZ i tried running it even at 5 MHZ but it give an output in post route simulation , behavioural works fine though.
and as u can see in the code , the fpga doesnt do anything except take input and get it out from output .. thats it. And i dont know where...
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