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shift left +std_logic_vector
PLEASE HELP ME WITH THIS CODE...I GET some weird error in this code...
U can even try pasting the code in any vhdl s/w n check..i work with xilinx ise!!!
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WARNING:HDLParsers:3458 - Because of erroneous VHDL in VHDL file c:\xilinx\bin\123/123.vhd, automatic...
Hey guys...well, im in a soup....and i need help quite urgently!!!
I had a post about this same topic b4...quite sometime back...
It is about this async system that i plan to design. The idea was to design an async ALU....a simple one albeit...but one which cud demonstrate the gr8 possibilities...
hey nand_gates..thanks a lot for showing interest and helping me with my project.
sorry for this but i got this one last problem...i dont quite know verilog the way i know vhdl and hence i really cant totally comprehend the test_bench that u've provided.
if u cud plz suggest any way to convert...
yeah..right ..i think i shud have done the first time itself...haha
ok...this is the link..it's a rapidshare link/..
**broken link removed**
it's actually a collection of all my project files....
proc is the main vhd file---my simple processor...
i havent included my test benches 'cause i...
wel...the clear signal i use is generated by completion of an instruction.
The project is a simple processor, implemented using the basic idea presented in morris mano "digital design"...where a timing decoder is used to generate a sequence of time cycles during which a given micro-instruction...
thx for the prompt reply...i tried the high pulse on clr and it worked just liked u said it would.
however, i still have a problem 'cause the upcounter( 2bit in this case) is supposed to work as an input to a decoder(2to4) to generate a timing cycle sequence T0,T1,T2,T3.
Now,Clr signal is...
modelsim tri1
hello..
i have this problem with a vhdl code when i try to simulate it in modelsim.
The code is for a simple counter ...link to it..
h**p://toolbox.xilinx.com/docsan/xilinx8/books/data/docs/xst/xst0018_5.html
when i try to run it in modelsim and force a value to "clear" i/p ,i...
well....i mean....normally in async systems...the whole adder or multiplier can be built as an asycn system....but also...we can use the blocks for each operation and then maybe use Hand shaking signals to pass on the results ...i mean communicate.
u cud chk any literature on async systems and...
hey guys...
well...i've finally begun work on my asynchronous ALU...while add/sub seems sorted out for now...i need some help as to how to begin with a multiplier...i dont plan to integrate a divide unit.
Also, while there r ieas to directly build an async add/sub systtem...i recently cam...
hi guys.....after some hectic work....i'm back at my own work.
I need to work on a project for my final graduation .After long thought and discussions, i have come to the conclusion tht i can work on a project in the field of "ASYNCHRONOUS CLOCKLESS UNITS"......basically, i wud like to work for...
Hey guys!!!!
well, i'm a nwebie at vlsi. We r expected to perform a basic project in class on an FPGA kit.
i have decided to perform the following project.
h**t//:www.fpga4fun.com/PongGame.html
Now, i need some help as regards to the way i proceed in implemeting the code in XILINX iSE.
I...
verilog wait until
thx a lot pal.......i cudnt quite thank u enough......
dont mind if i bug u in the future ......'guess i'll get cracking with it now!!!!
to_stdlogic
hey guys, i need help urgently.
i'm a newbie at vlsi and as far as i'm concerned i've made myself fairly able at vhdl. i'm planning to reaslise the following project .This happens to be my first project with vhdl anyway.
link:: h**p://www.fpga4fun.com/PongGame.html
Now, i need u...
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