Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by Tetra

  1. T

    spartan pin LOC problem

    assign pin virtex Dear TPL71 I avoided the special pins in my design. and to be sure I made a small NAND gat design and I ssigned the three pins into general I/O pins and I got the same error. Dos anyone passed the design flow Leonardo -- file.edf --> alliance ---> file.bit on win2000...
  2. T

    spartan pin LOC problem

    pinloc regarding the device it is spartanII 100K gate and -5PQ144 specify speed grad and packaging so it will not change our setuation as the folw stop at certain step. any way I'm sure that the LOC syntax is right as the translate step passed. regarding "XI_MAP_LOCWARN" thats right, it is...
  3. T

    spartan pin LOC problem

    error maplib:30 Regarding the device is SpartanII XC2S100-5PQ144. regarding the Case and pin number, I did an experiment that a NAND fate and assigned the 3 terminals with I/O ports and I got the same results.
  4. T

    spartan pin LOC problem

    xil_map_locwarn The problem summrized in the following steps 1- I need to assign certain pins pf spartan 2 device so I used different methode to do so (Constrains editor, ucf file gnerated from leonardo, attribute in VHDL file ) all methode gave successful results and the Constraint Editor see...
  5. T

    assign certain pin location in VHDL code

    Dear tpl71 thanks for your support. I tried the solution you specify and it done well with single line signal. I tried to treat a bus with the same idea by writing attribute Location of Address_Bus_H(0) : signal is "112"; but I get an error message "C:/~/adapter.vhd", line 65: Syntax Error...
  6. T

    How can I specify the division ratio in xilinx DLL?

    division ratio in DLL How can I specify the division ratio in xilinx DLL?
  7. T

    how to design a 74HC245 using verilog?

    if you target actual design, you can instantiate Tri-state buffer from the target FPGA and do the required connection. I see a lot of xilinx application do so and do not use HDL description. to avoid different synthesizer methodology.
  8. T

    Delay configuration completion by DLL

    I know that, so should I tie this pin to external output pin and control the ~INT pin to delay the DONE signal ?, or there is an internal methode ?
  9. T

    Delay configuration completion by DLL

    I read in xilinx data sheets that I can delay the configuration of the FPGA until an internal DLL reach lock state how can I do that.
  10. T

    Problems with power supply in HC11 circuit

    I think the remaining problem of digits disappearing return to your ground scheme. I had a similar problem but with 7-seg one.When I invesyigat it I found that the ground of 7-seg section lay at the end of a ground line that hold high current in some cases of operation, so the ground of the...
  11. T

    video signal distributor needed

    As a cheap solution you can use cascaded passive splitter. as splitter is a passive one attenuation will be done, if this attenuation is accepted then keep it, and if not go to an active solution as other friend describe.
  12. T

    555 simulation on ORCAD9

    simulation du 555 I tried to simulat 555 circuits on Orcad9.0. The Anl_Misc contains three Model 555B, 555C, 555alt. 555B only passed without errors but simulation output do not work at all. anyone can help?
  13. T

    Best way to build big LUT

    That is right
  14. T

    Best way to build big LUT

    I want to build a big LUT in VHDL. What is the best way to build it without sacrifizing the VHDL generality (i.e without using technology specific memory) regards
  15. T

    assign certain pin location in VHDL code

    attribute pin assign in vhdl Can I use certian VHL attribute to direct the synthesizer to assign certain Input or output pin to certain pin location on the target FPGA ?
See more

Part and Inventory Search

Back
Top