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Hi everybody,
I've learnt that the development board of the Altera Stratix which is sold by MJL contains the USB host SL811 chip from Cypress.
Since I am working with another FPGA, Xilinx Spartan III from XESS, I was wondering if anyone has the first mentioned board and would be so kind to...
Re: serial port
Just look for "miniterm" on the web. It is a simple terminal client for linux.
Since it is opensource, you can learn and modify as you will.
Documentation :
**broken link removed**
Link for a complete collection with examples...
vhdl 2 dimensional array
since your multidimensional array typically represents a RAM memory there are two possible usages .
as we suppose that you declared your type and signal identically as other users suggested you :
type memory is array (INTEGER range <>) of std_logic_vector(7 downto...
Re: FPGA and USB host
Good morning to all USB developers, Farhada and Ace-X !
At last I got rid of these glitches by two reasons :
first, I realized the changes in my VHDL code as you gave me pieces of advice and at the end I changed a bit the combinatorial process so that the outputs are...
Re: FPGA and USB host
Hi Farhada and all USB developers,
Many thanks for your interest and quick answer. Now I have some more clear ideas.
In order to build my development platform, I wanted to realize the example which is in the datasheet of the Cypress - i.e. the write and read RAM cycle...
FPGA and USB host
Hi,
I have to drive a Cypress USB host SL811HS with a FPGA.
My FPGA is a XESS development kit with a Xilinx Spartan3, 1M gates.
As you may know, the Cypress requires an 8 bit data bus and 6 pins for controlling.
I have decided to syntethize all this controlling stuff with...
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