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Recent content by tenya

  1. T

    Specman Tool: Handling codes with module instantiations

    Check for Design Verification with 'e' by Samir Palnitkar. Alternatively you can use the documents or LRM in $SPECMAN_HOME/docs
  2. T

    How to dump out a vcs file in Verilog simulation?

    Re: Verilog Task Function initial begin $dumpfile("top.vcd"); #100 $dumpvars(0,top); // Here Replace #100 by whatever time you need. end
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    What is the best software for VHDL?

    Best thing is to download modelsim, send a license request and use it. You can use it for editing, simulating your designs. For Complete Design flow use Xilinx-ISE8.1
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