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the transistor sizing is done only to the width of the transistor not for the length, the length is fixed based on the technology. If it is 90nm then the length of the transistor is 90nm so it is fixed for the transistor in that 90nm technology no varying is done.
hi i have a problem regarding the path groups, after completing the cts stage when checking for summary of the voilations using the report_qor, it is giving the report only for the REGIN, REGOUT, and SCANCLK paths not for Main CLOCK, i didnt change any thing in the scripts it was giving in the...
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