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Recent content by teem

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    Injection Locked Frequency Divider

    Hi, I draw a simple injection locked frequency divider. Parameters in design are as follows: Technology: tsmc 0.18um RF. M0,M1: NMOS Width/Length/NF(number of fingers)=3um/0.18um/6 M2: NMOS Width/Length/NF=3um/0.18um/9 Inductor: center tapped. Width/Space/Radius=9um/2um/51.8um Input: 26GHz sin...
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    Miller Frequency Divider Design

    Dear, I have to design an inductively-loaded Miller divider, schematic is as below figure shown. The Vout is fed back to M3 and M4, Vin is 26GHz, Vout is 13GHz. Technology I used is tsmc 0.18um. Could anyone explain me how to start with? How to determine the size of MOS? What’s the optimum bias...
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    How to Plot the Outputs in Ocean

    Dear All: I am new to ocean script. I am using foreach loop to change the value of a variable, run the simulation and calculate the output which is a single value. Codes are like below foreach(i ‘(1 3 5) desVar(“variable” i) run() voutAt10ns=value(VT(“/vp”) 10n) ;one value for each...
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    Flicker Noise Noise Folding Question

    Dear Friends: Flicker noise is infinite at DC. If I pass flicker noise through an on/off switch with switching frequency w, what the output spectrum would be? Would the spectrum be infinite at w, 3*w, 5*w…etc? Thanks and have a good day.
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    Spectrum Analyzer Output

    Hi, Allow me to ask a simple question that I cannot figure out. If the input wave form to spectrum analyser is as below. What would be the output waveform with respect to the resolution bandwith setting? Besides, which kind of tools is easiest to go above test? Thanks...
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    VerilogA VCO Model to Simulate Phase Noise

    Hi, I tried to build a verilogA VCO phase-domain model by referring to Ken Kunder's paper. Then I have no idea how to start with, thus I set up a simple testbench as below image shown. I chose "noise" analysis and run. Spectre then showed error indicating "Matrix is singular (detected at...
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    How to probe the voltage of internal node defined in model card?

    Hi, I use tsmc18 RF model to model my NMOS. The RF model of the NMOS itself is a sub-circuit. When I run pss with spectreRF, it showed warning for the NMOS: "M0: Missing bulk-source diode would be forward biased", but I actually tied bulk and source together and they are tied to ground. I run...
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    Virtuoso ADS Output Expression

    Hello, I setup below outputs to calculate the equavilent parallel R and L by doing one-port SP analysis in Virtuoso ADS. freq=xval(aaSP(1 1)) Lp=-1/imag(YP(1 1))/(2*acos(-1)*freq)) Rp=1/real(YP(1 1)) It showed error message: ("*Error* eval: unbound variable"...
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    RLC Extraction from S-parameter Analysis

    Hello, If I do SP analysis in spectreRF for a frequency range, how can I get its equivalent series R,L,C and parallel R,L,C? Is there any suggested fundamental book I can refer? Many thanks.:razz:
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    PSD of The Phase of the Oscillator

    Hi, In Phillips' paper: https://www.designers-guide.org/Theory/cyclo-paper.pdf I am quite baffled by his comment "impulse response of the phase deviation phi(t) can be approximated with a unit step s(t)". Why and how to explain that? Further, how to derive equation (6) from equation (5)...
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    How to get Ceq and Req of a node?

    Hi, I am newbie on circuits. I am trying to get the equivalent R and C of a designated node with respect to frequency. First attached image is my example, it’s a simple CS amplifer, and I use below ocean script to calculate equivalent Req and Ceq: … analysis(‘sp ?start 10M ?stop 50G ?ports...
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    How to Convert Transimission Line to Equivalent Lumped Element

    Hi, Below is link talking about the PLL operating at 75GHz: http://cc.ee.ntu.edu.tw/~jrilee/publications/75G_pll_J.pdf Could any experts explain me how to convert the VCO loaded with lossy transmission line to equivalent VCO loaded with lumped inductor? I mean, how to calculate the equivalent...
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    PLL System Behavior Simulation on Transistor Level

    Hi, We generally simulate PLL system behavior and calculate loop parameters first by using tools like MATLAB or others, then start to realize the circuits. After that, we check the step response or phase noise on transistor level of the PLL with tools like HSpice or Spectre. Here are my...
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    Questions on jitter modeling in bang-bang CDR(Clock Data Recovery) circuits

    Hi, Attached is paper from IEEE talking about jitter modeling in bang-bang CDR circuits. I am quite confused with the comments from authors and do not understand how to come out equation(1) and equation(3). Could any experts explain these 2 equations in detail? Thanks very much in advance.
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    Current mirror questions - wilson vs. cascode

    1. But as I know, in the figures, wilson mirror has the same Rout as cascode mirror. 2. I am really confused about the difference if I diode connect Q12 instead of Q13 in the bias circuit. Anyone can help explain? Thanks.
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