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Sun_ray,
There are no short cuts for FIFOs. 1st you have to understand the architecture of a simple fifo that passes gray encoded pointers across the async boundaries. Then you can draw timing diagrams for the read/write pointers. FIFO's are very simple but you have to understand the...
Your question needs to be more specific. For instance, if you have full/empty flags, your fifo depth can be '1'. It will stall the writes, but it will still 'work.' As for NO full/empty flags, it depends on the clock frequencies and how often you can push and pop the fifo. Also, is the...
In the link that I provided, the "32-bit Register" example shows how to reset your flip flop. Also look at the "32-bit Register Testbench," it shows how to instantiate your "nzri" module in the testbench. That's all you have to do.
I think you need to do some more studying/reading. These are very,very basic verilog questions that can be found on most websites. Typically you should have 2 modules, one module contains the design and the second module contains the testbench. The design module should be instantiated in the...
In your 1st posting, you state, "...write a verilog code that will accept serial data and clock ...". Your (synthesizable) verilog module will simply list 'clock', "reset", and "serial_data_in" as inputs and "nrzi_data_out" as an output - same as the top level module that you have seen in...
Start with a list of functionality that you intend to support. Not everything in the spec is required. If you want to include APB and AHB with AXI interconnect, then yes, you would need some sort of bridging function. You also need to look at what architecture you intend to support (i.e...
Thank you 'lostinxlation.' If the latency of all clock trees is less than 1/2 a "shift clock cycle", then there is no chance of metastability. I don't fully understand the clocking waveforms for scan shift and capture with respect to "At Speed" tests and how the lock-up latch will work in...
This is a relatively novice question (i.e. I'm a novice at running DFT tools), but a chip could have quite a few lock-up latches. How would you go about determining a single "shift clock frequency" that works for all scan chains? It doesn't seem pausible that you would just 'change' the clock...
"verilog mode" will work if the signal names are consistent. I believe you can run it in a batch mode so it will work from bottom up. Just search for "verilog mode" on the internet.
assuming that their are two clock domains (clk1 and clk2) separated by a lock up latch, don't you also have the restriction that the rising edge of clk2(later domain in scan chain) must not violate setup and hold of the Latch output signal?
To be clear, you cannot pass a signal from one...
you could use: run() is also { } to start a process at the beginining of simulation
in that process, synchronize to the rising edge of pll_clk and emit a new event pll_clk_1st_rise
If the DQS is shifted until it samples a high clock in the DRAM (for write leveling), how is the relationship between DQS and DQ maintained while the DQS is changing phase? Is there a DLL for each memory controller DQ that uses DQS as a reference?
Your english is tough to understand....but jitter comes from many sources (pll noise, inter-symbol interference, x-talk, etc.). Jitter is usually measured over a period of time to hit all scenarios with respect to ISI. If you want specific answers, you may need to ask a more detailed question.
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