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In behavioral verilog code below, what happens if signals a,b rises at the SAME time?
always@(posedge a)
begin
if (b==1) do this
else do that
end
In modelsim: b takes value 0 and 'do that' occurs. In iverilog, b=1 and 'do this' occurs. So, looks like it is not standardized across compilers...
Thanks for the reply.
Process B(processing) is assumed to be much faster than A(receive data). Reason being that process B runs on a data clk which is much slower than the system clk that A runs on.
- - - Updated - - -
A valid data word is indicated by another signal, transmit_start.
B should...
I am trying to code a system in behavioral verilog that has 2 processes running concurrently. One is a serial input buffer that continuously monitors the input line for valid data (let's call this process A). The other is a process that kicks off when valid data is detected and passed to it. It...
Tried opening some of my previous schematics in cadence and found that I could not edit them.
All the edit functions'/buttons such as "add wire", "add instance", "delete", etc.. are gone from the menus. If I press the bindkeys to try initiate, say, a delete, an error msg shows on icfb...
Where can I find the ahdlLib? I don't see that in my Component Browser's Library drop down.
Or anybody with an idea on how to get an ideal comparator into my Cadence design? Thanks!
Ok. Thanks. We are trying to P&R with a hierarchical netlist and running into placement errors. We think it has something to do with this code in our .LEF
SITE CoreSite
CLASS CORE ;
SIZE 0.56 BY 5.7 ;
END CoreSite
What does this do or define?
Thanks for the reply. We found the problem. The models were not correctly defined and the runs were going into recursive procedures. Thanks again for the offer to help!
-TB
Hi,
I extracted a netlist from my schematic and fired off hspice. It's a 512b sram design and still running after 12 hours.
My question is:
How do I know it really IS taking that long or the simulation is not converging? Or some other issue..??
Thanks,
TB
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