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Recent content by tayyab786

  1. T

    Need logic that implement in Verilog coding

    There are seven d/f inputs from seven different module are received by one module..an array have some value is already present in the that module. Now the first index value of array is assign to those module which has largest input value... and 2nd index value of array are assign to those...
  2. T

    is nested for loop supported in verilog

    following code not give desired ouput the desired output is random number having length 510, instead of given random number it will give following pattern parameter length = 8 ; parameter [1:length-4] initial_state = 4'b1101; //for lFSR parameter [1:length-4] Tap_coefficient =...
  3. T

    if (max[M:0] > value) in verilog...where M is input...Alternative

    get error on this statement if (max[M:0] > value) where M is input... i know we cannot declare a value in an array that can change at run time ....any alternative for this statement
  4. T

    Generate desired random number in range in verilog

    i want to convert lfsr_output into in desired range and it does not take more than 2 cycle.. for 8 bit lfsr it max output is 255. now when user enter a value e.g 35 it convert 255 into 0-35 range in such a way that it randomness cannot distrube . suggest any method other than y=ax+b
  5. T

    Generate desired random number in range in verilog

    [Moved]range of lfsr depend upon input value hi i have written the code of 8-bit lfsr in verilog. its work fine e.g it randomly generate value from 1-255 now i want to transform this code to general lfsr e.g if user put 35 it generate random value from 1-35. and so on
  6. T

    [SOLVED] logic : give value in which require decimal number represent

    language is verilog hardware is fpga decimal value is integer value the input is in decimal value ( for hardware i know its in binary format but for simulation its decimal value ) its does't matter range depend on user but not exceed with maximum value e.g max value is 255 so user have...
  7. T

    [SOLVED] logic : give value in which require decimal number represent

    hi all i need a logic that give me value in which require decimal number represent e.g 1: if input is 32 it give me value 5 as 32 represent in 5 bit 2 if input is 42 it give me value 5 as 42 represent in 5 bit 3 if input is 128 it give me a value 7 as 128 represent in 7 bit and...
  8. T

    FPGA Vertex -6 ML605

    i already see their data-sheet of xilinx vertex6 ml605...There are two FMC-HPC connector present in the board. the question is can this connector use as GPIO?
  9. T

    FPGA Vertex -6 ML605

    GPIO of FPGA Vertex -6 ML605 which port of FPGA vertex 6 ML605 use as a GPIO like in audino and ressbarry pi. There are FMC-HPC connector present in the board. can this connector use as GPIO?
  10. T

    Generate desired random number in range in verilog

    Thanks klaus. This approach almost 70% solve my problem
  11. T

    Generate desired random number in range in verilog

    for division we require floating point division. But as i mentioned this is not problem. can you give me some example which will fit in current criteria
  12. T

    Generate desired random number in range in verilog

    Not fit in current criteria e.g e.g in 3 bit LFSR, min number is 5, now next time suppose lfsr generate 3, Now according to your logic min+(lfsr_output/max value) gives 5+6=11 which is not in range. also it require floating point division which is not supportive in some FPGA, but division is...
  13. T

    Generate desired random number in range in verilog

    I am trying to generate a desired random number in range. for random number we use LFSR alogorithm. Now I want...First time LFSR output become the min number . Now in next cycle the random number should greater than previous LFSR number and so on, but it also not exceed with max value. max...
  14. T

    [SOLVED] Latches create in verilog code

    Yes FVM you are right. I alright solve that problem.
  15. T

    [SOLVED] Latches create in verilog code

    Re: latches create in verilog code i know that else statement is not necessary but it actually sure that not to create latches. because missing if else statement cause latches... i also initialize cts with zero but same warning show. the complete code is module...
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