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Recent content by tanvirnsuer

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    Problem with verilog file (regarding $readmemh)

    e: Problem with verilog file (regarding $readmemh) I have changed a little bit in the $display line: $display("f=%h, a=%h, b=%h, y=%h, zero=%h, vec=%h",f, a, b, y, zero, vec[i]); I have added vec[i] to display. now from the results window, i got the picture just like this: **broken link...
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    Problem with verilog file (regarding $readmemh)

    Yes, it exits. I have written the location exactly where it is. - - - Updated - - - yes it exits. Thanks.
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    Problem with verilog file (regarding $readmemh)

    Hi, I am trying to use $readmemh in verilog,but i am getting no error. But, it displays xxxxxxxx value for input and output where I want hex numbers. My code is as: module testbench; reg [31:0] a,b; reg [2:0] f; wire [31:0] y; wire zero; parameter vecs = 22; alu alu0...
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    USB 2.0 Verilog Coding problem

    Hello there. I found this USB 2.0 code from here: https://opencores.org/project,usb,overview I am facing some problem in simulating it. It shows no error to compile or simulate in Modelsim but shows no waveform. :sad: Can anyone help me how i can get waveform using this files? (by using...

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