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I used rcOut to get spf and spef file. But I prefer to get the interconnect delay information.
I saved the timing report, but I only see the gate delays (shown as following).
How does CTE calculate the intrconnect delay?
Path 1: MET Path Delay Check
Endpoint: N421 (^)
Beginpoint: N82 (v)...
After P&R in encounter, I saved the timing reports. However, in postRoute_in2out.tarpt, I only see the delay of every gate in each path.
There is detailed RC information, the interconnect delay should be calculated during timing analysis, where is it?
What engine is called by encounter for...
I used encounter to do place and route, then I get the timing files and .spf and .spef files of the layout information.
But I prefer to have .rspf (reduced standard parasitic format) file because I need to know the pi model of every node.
How to get it?
I checked rcOut. It doesn't support...
When using RTL compiler.
I used the following setups:
set_attribute wireload_mode top
set_attribute interconnect_mode ple
set_attribute library {nldm.lib}
set_attribute lef_library {**.lef}
set_attribute cap_table_file {**.capTbl}
........
synthesize...
I tried report timing -to [all_outputs] > timing.rpt, but in the timing.rpt, I still got one critical path timing.
Actually, I want to know every gate load capacitance the RTL complier used for a big circuit. Then I can check the accuracy of NLDM w.r.t. spice/spectre simulation.
is there...
in Hspice, LX18-LX34 can be used to get the parasitic capacitance of a MOS device.
such as LX34(m)=CDSBO.
I read some examples, it seems that I have to run .dc or .tran if I want to get those 9 caps.
What about if I just want to use
.op??
I tried it, but I got nothing...
The constrain is determined according to the requirement of design. So, it should be decided by people...
For digital circuits, the timing must meet the corresponding requirement otherwise the results from the circuit will be erroneous.
sdf can be used to check the functionality of the circuits...
ccs: current source model from synopsys
ecsm: effective current source model from cadence
nldm: nonlinear delay model
they are used for static timing analysis.
During timing analysis, the .lib or .db(Primetime) are needed. differen .lib or .db file use different gate delay models like ccs.
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