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Document says
"Automatically calculates VCO frequency for
primitives with an oscillator, and provides
multiply and divide values based on input and
output frequency requirements"
does it means that i need to fix other parameters (like CLKFB_MULT_F and DIVIDE_DIVCLK) to get the VCO frequency...
Can any1 help me . y im not getting shifted clock at output?
here is the code for it
module test(input clk, rst, inc,ref_clk, enable, output reg s_clk1, s_clk2, output done, clk_valid
);
wire temp1, temp2;
always@(posedge ref_clk)
begin
if(rst)
begin
s_clk1<=0...
I am using 2nd code. but i m having warnings in it. and when i simulate it. i m not geting anything at output.
WARNING:Xst:2211 - "ipcore_dir/memory.v" line 38: Instantiating black box module <memory>.
WARNING:Xst:1780 - Signal <memory> is never used or assigned. This unconnected signal will...
I am trying to read/ write a file from mem.
here is my code. I have an error "" if any1 can help me.
ERROR:HDLCompilers:247 - "wr_file.v" line 34 Reference to vector wire 'data_out' is not a legal reg or variable lvalue
ERROR:HDLCompilers:106 - "wr_file.v" line 34 Illegal left hand side of...
I ma trying this code for writing a file but cant include data.v file. I have write data file in a doc and saved it as '.v' file but when i add it to stimulus it givess me error
module readmemh_demo;
reg [31:0] Mem [0:11];
`include "data.v"
integer k;
initial begin
#10...
I am trying this code for reading a text file. but when i simulate it, my output at Mem is XXXXXXXXXX . can any1 help me whr i am rong??
module readmemh_demo;
reg [31:0] Mem [0:11];
initial $readmemh("data.txt",Mem);
integer k;
initial begin
#10;
$display("Contents of Mem after reading data...
HEllo all,
How can i use output of a shifted clock as a clock input for a new combinational logic??? Im trying to use the 90 degree shifted clock as a clk input for any other logic??
always@(posedge 90clk)
begin
---
---
end
if i do so then my output is unknown. if any1 could help...
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