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Recent content by Syswip

  1. S

    how to detect ADC saturation

    Hi forum. I have digital signal directly from the ADC. I need to design digital circuit to be able to detect, if ADC is saturated or no. Is there any algorithms to implement this? Or the only way is to check maximum and minimum values? Thank you very much.
  2. S

    FFT scaling for hardware implementation

    Unfortunately your reference does not answer my questions.
  3. S

    FFT scaling for hardware implementation

    Hi forum, Do we really need to scale FFT for hardware implementation? Up to now I found 2 situations where scaling has advantage: 1. It will save the logic because the internal word length remains unchanged. 2. The twiddle factor multiplication error will be less. The scaling also can be...
  4. S

    FFT absolute error calculation

    Hello, I'm looking a way to calculate my fixed point FFT absolute error. I don't use any scaling (increasing the word length after each stage) in my implementation. But there is still error due to a fixed point multiplication with twiddle factor. Is there a way to calculate absolute error...
  5. S

    DFT output maximum size

    Thank you very much guitarguy12387. I'll try to understand the theory. Bests, Tiksan.
  6. S

    Area report: ASIC Design

    Can be nothing strange. You changed the library and the tool synthesized in different way. It is OK do not worry.
  7. S

    DFT output maximum size

    Thank you guitarguy12387, Could you please give me the source of this equation? bxk = bxn+ log2 (maximum point size) +1 Why +1? I want to understand. Thank you very much, Syswip.
  8. S

    Area report: ASIC Design

    Hi Subhash, Usually your frequency should be increased and area should be decreased for 65 nm. But it also depends which kind of library you use. For example if you use low power 65 nm technology your frequency may go down in this case. Bests, Tiksan
  9. S

    DFT output maximum size

    Hi folks, As I know the output of the DFT is N times more than input. I'm doing 16 point DFT. My input samples are in range -32768..32767. It means that the maximum value of the output must be 32767 * 16 = 524272. But I found the input sample sequence which DFT result is more than the maximum...
  10. S

    How to calculate FFT core SQNR?

    I found the solution: SQNR = 10*log((M0*M0+M1*M1+M2*M2+.......+Mn*Mn)/((M0-R0)*(M0-R0)+(M1-R1)*(M1-R1)+(M2-R2)*(M2-R2)+.......+(Mn-Rn)*(Mn-Rn))) I hope this will be helpful for others. Bests, Tiksan.
  11. S

    How to calculate FFT core SQNR?

    Where are FFT experts?
  12. S

    parallel multiplier of 8 bit data

    Binary multiplier - Wikipedia, the free encyclopedia Multiplication algorithm - Wikipedia, the free encyclopedia Booth's multiplication algorithm - Wikipedia, the free encyclopedia ... ... ...
  13. S

    How to calculate FFT core SQNR?

    Hi forum, How to calculate FFT core SQNR? Sounds very easy but seems it is not. I have a Verilog RTL core for FFT. I have a very accurate reference model for FFT. Let's assume that my RTL core outputs are R0, R1, R2.......Rn. And reference model outputs are M0, M1, M2.......Mn. Having these...
  14. S

    trouble simulating a possible tri state buffer

    Of course it will not work. You must assign Z state to the w_data when it is output from your module. assign w_data = r_rw ? r_data: {16{1'bz}} ;
  15. S

    trouble simulating a possible tri state buffer

    How did you connected these modules in your test bench?
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