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Hai rberek,
Can I write the list of memory contents with a simple header in notepad? How to save it by .coe? Or there is any free software to create .coe file? Thanks for reply
Hai all;
I try to do some tutorial about create a ram using coregen in xilinx. I follow the steps listed in the pdf file (I get from google). However, I didn't have the .coe file and I try to create my own .coe file. My question is how to create .coe file? And if possible, how to convert a .txt...
Hai rberek,
I have fpga single board RIO (sbRIO 9632) with Spartan device. In Labview there is tool/vi that I use to select this fpga (sbRIO9632). Moreover, labview allow user to use a bitfile for take part in the project. I have the fpga target in labview, but I don't have the fpga target in...
Hai rberek and mrflibble,
Actually I used ISE to write some process (vhdl code). Then, I used another software which Labview to build the whole process and insert the bitfile of the vhdl code. Labview will check the syntax error of the bitfile and download it in fpga when I run the project. I...
Hai all,
I have fpga board with spartan device (xc3s2000) and I use Xilinx ISE Design Suite 14.2 that I download from internet. My problem is when I select device xc3s2000 in ISE and compile the vhdl code, this error message come out:
ERROR:Security:12 - No 'xc3s2000' feature version 2012.07...
Hai TrickyDicky,
Actually, I use std_logic_vector at all my operation (others port map). That why I casting it back to the same data type. Btw, thanks for reply, I understand about the adding zero in the line code now. Thanks in advance.
Hai FvM,
Below is the data types of the signals:
signal dcto_1 : STD_LOGIC_VECTOR(DA_W-1 downto 0);
signal romedatao : array(0 to 7) of STD_LOGIC_VECTOR(13 downto 0);
constant DA_W : INTEGER := 22;
I understand now why the sum is 384. As you said concetrating a zero at the...
Hai all,
I have confusion with resize function in vhdl. I have write a line of code as below:
if even_not_odd = '0' then
dcto_1 <= STD_LOGIC_VECTOR(RESIZE
(RESIZE(SIGNED(romedatao(0)),DA_W) +
(RESIZE(SIGNED(romedatao(1)),DA_W-1) & '0'),
DA_W));
When I...
Hai TrickyDicky,
Did you mean an input 0-16 will give a same LUT value? Then 17-24 will give another LUT value?
I already build the LUTs (256 entries) and connect all the 8bits of the X as the address. It successfully run in ModelSim for testbench. However, I don't know how to check whether...
Yes, I have 16 entries (with 4 constant). Btw, how to put a right values into a right parts of the LUT? I know the general steps/ways to build the ROM as what I do now (split to 2 LUTs), but I don't know the complex LUT. Hope you can advices.Thanks in advance
Hai TrickyDicky,
Did you mean (4 downto 1) for address and bit (0) for even/odd select? I split the table due to the mathematical equation as I show at the previous thread. I'm not sure if I combine all the 8 constant into one table I will get the right results. Thanks in advance
Hai TrickyDicky,
I build 2 4-entry LUT. As you said, I use the LSB (3 downto 0) of the input data (7 downto 0). How to select either LUT1 or LUT2? Can use bit (4) of the input data to make the selection? Thanks in advance
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